ATF1502BE-5AX44 Atmel, ATF1502BE-5AX44 Datasheet - Page 10

• Manufacturer Part Number: ATF1502BE-5AX44
• Description: IC CPLD 64MC 1.8V 44-TQFP
• Manufacturer: Atmel
• Series: ATF1502BEr

Specifications of ATF1502BE-5AX44

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Macrocells: 32
• Number Of I /o: 32
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Features: CMOS/TTL Compatible
• Voltage: 1.8V
• Memory Type: EEPROM
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

6. JTAG-BST/ISP Overview
6.1
10
JTAG Boundary-scan Cell (BSC) Testing
ATF1502BE
All ATF1502BE devices are initially shipped in the erased state, thereby making them ready to
use for ISP.
Note:
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1502BE. The boundary-scan technique involves the inclusion of a shift-register stage (con-
tained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing methods. Each input pin and I/O
pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The TAP controller
i s a u t o m a t i c a l l y r e s e t a t p o w e r - u p . T h e f i v e J T A G m o d e s s u p p o r t e d i n c l u d e :
SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1502BE’s ISP can be
fully described using JTAG’s BSDL as described in IEEE Standard 1149.1. This allows
ATF1502BE programming to be described and implemented using any one of the third-party
development tools supporting this standard.
The ATF1502BE has the option of using four JTAG-standard I/O pins for boundary-scan testing
(BST) and ISP purposes. The ATF1502BE is programmable through the four JTAG pins using
the IEEE standard JTAG programming protocol established by IEEE Standard 1532 using 1.8V
LVCMOS level programming signals from the ISP interface for in-system programming. The
JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG
control pins are available as I/O pins.
The ATF1502BE contains 32 I/O pins and four input pins. Each input pin and I/O pin has its own
boundary-scan cell (BSC) in order to support boundary-scan testing as described in detail by
IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan registers and
up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the
macrocells. The BSCs in the device are chained together through the capture registers. Input to
the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin.
Capture registers are used to capture active device data signals, to shift data in and out of the
device and to load data into the update registers. Control signals are generated internally by the
JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells is shown
below.
For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”
application note.
3492A–PLD–12/05