ATF1502BE-5AX44 Atmel, ATF1502BE-5AX44 Datasheet - Page 4

IC CPLD 64MC 1.8V 44-TQFP

ATF1502BE-5AX44

Manufacturer Part Number
ATF1502BE-5AX44
Description
IC CPLD 64MC 1.8V 44-TQFP
Manufacturer
Atmel
Series
ATF1502BEr
Datasheet

Specifications of ATF1502BE-5AX44

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Macrocells
32
Number Of I /o
32
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Features
CMOS/TTL Compatible
Voltage
1.8V
Memory Type
EEPROM
For Use With
ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATF1502BE-5AX44
Manufacturer:
Atmel
Quantity:
10 000
Figure 1-3.
1.1
1.2
4
Product Terms and Select Mux
OR/XOR/CASCADE Logic
ATF1502BE
ATF1502BE Macrocell
Each ATF1502BE macrocell has five product terms. Each product term receives as its inputs all
signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to the
macrocell logic gates and control signals. The PTMUX programming is determined by the design
compiler, which selects the optimum macrocell configuration.
The ATF1502BE’s logic structure is designed to efficiently support all types of logic. Within a sin-
gle macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR
sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to
as many as 40 product terms with minimal additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions.
One input to the XOR comes from the OR sum term. The other XOR input can be a product term
or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selec-
tion. For registered functions, the fixed levels allow DeMorgan minimization of product terms.
The XOR gate is also used to emulate T- and JK-type flip-flops.
BURIED FEEDBACK
TRIGGER
SCHMITT
3492A–PLD–12/05

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