ATF1502ASL-25AU44 Atmel, ATF1502ASL-25AU44 Datasheet - Page 4
![IC CPLD EE LP 25NS 44-TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATF1502ASL-25AU44
Manufacturer Part Number
ATF1502ASL-25AU44
Description
IC CPLD EE LP 25NS 44-TQFP
Manufacturer
Atmel
Series
ATF1502AS(L)r
Datasheet
1.ATF1502ASL-25JU44.pdf
(26 pages)
Specifications of ATF1502ASL-25AU44
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
25.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Macrocells
32
Number Of I /o
32
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
4.75 V ~ 5.25 V
Memory Type
EEPROM
Family Name
ATF1502ASL
# Macrocells
32
Number Of Usable Gates
750
Frequency (max)
60MHz
Propagation Delay Time
25ns
Number Of Logic Blocks/elements
2
# I/os (max)
32
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
For Use With
ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATF1502ASL-25AU44
Manufacturer:
ATMEL
Quantity:
592
Figure 1. ATF1502AS Macrocell
Product Terms and
Select Mux
OR/XOR/
CASCADE Logic
Flip-flop
4
ATF1502AS(L)
Each ATF1502AS macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to
the macrocell logic gates and control signals. The PTMUX programming is determined by the
design compiler, which selects the optimum macrocell configuration.
The ATF1502AS’s logic structure is designed to efficiently support all types of logic. Within a
single macrocell, all the product terms can be routed to the OR gate, creating a 5-input
AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be
expanded to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows
polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of
product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.
The ATF1502AS’s flip-flop has very flexible data and control functions. The data input can
come from either the XOR gate, from a separate product term or directly from the I/O pin.
Selecting the separate product term allows creation of a buried registered feedback within a
combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-
ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-
through latch. In this mode, data passes through when the clock is high and is latched when
the clock is low.
0995K–PLD–6/05