EPM3064ATC44-4 Altera, EPM3064ATC44-4 Datasheet - Page 36
![IC MAX 3000A CPLD 64 44-TQFP](/photos/6/70/67053/544-44-tqfp_sml.jpg)
EPM3064ATC44-4
Manufacturer Part Number
EPM3064ATC44-4
Description
IC MAX 3000A CPLD 64 44-TQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3064ATC44-4
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
4.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
34
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Family Name
MAX 3000A
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
250MHz
Propagation Delay Time
4.5ns
Number Of Logic Blocks/elements
4
# I/os (max)
34
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1160
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM3064ATC44-4N
Manufacturer:
ALTERA
Quantity:
14
Part Number:
EPM3064ATC44-4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 3000A Programmable Logic Device Family Data Sheet
36
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ZX3
XZ
SU
H
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
Table 23. EPM3256A Internal Timing Parameters (Part 2 of 2)
Table 24. EPM3512A External Timing Parameters
Symbol
Symbol
Output buffer enable delay, slow
slew rate = on
V
Output buffer disable delay
Register setup time
Register hold time
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low–power adder
Input to non-registered output
I/O input to non-registered
output
Global clock setup time
Global clock hold time
Global clock setup time of fast
input
Global clock hold time of fast
input
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
CCIO
= 2.5 V or 3.3 V
Parameter
Parameter
C1 = 35 pF
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(2)
C1 = 35 pF
C1 = 5 pF
(2)
(5)
Conditions
Conditions
Note (1)
(2)
(2)
Min
5.6
0.0
3.0
0.0
1.0
3.0
3.0
2.5
Min
2.1
0.9
-7
Note (1)
–7
Max
Speed Grade
7.5
7.5
4.7
Max
Speed Grade
9.0
4.0
1.2
0.8
1.6
1.0
1.5
2.3
2.3
2.4
4.0
Min
1.0
7.6
0.0
3.0
0.0
4.0
4.0
3.5
Min
2.9
1.2
-10
–10
Altera Corporation
Max
10.0
10.0
6.3
Max
10.0
5.0
1.6
1.2
2.1
1.3
2.0
3.0
3.0
3.2
5.0
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns