EPM570GT100C5N Altera, EPM570GT100C5N Datasheet - Page 12
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EPM570GT100C5N
Manufacturer Part Number
EPM570GT100C5N
Description
IC MAX II CPLD 570 LE 100-TQFP
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM570GT100C5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
76
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
1.8V
Memory Type
FLASH
Number Of Logic Elements/cells
570
Family Name
MAX II
# Macrocells
440
Frequency (max)
1.8797GHz
Propagation Delay Time
8.7ns
Number Of Logic Blocks/elements
57
# I/os (max)
76
Operating Supply Voltage (typ)
1.8V
In System Programmable
Yes
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1405
EPM570GT100C5N
EPM570GT100C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM570GT100C5N
Manufacturer:
INTEL
Quantity:
1 235
2–4
Logic Array Blocks
Figure 2–3. MAX II LAB Structure
Note to
(1) Only from LABs adjacent to IOEs.
LAB Interconnects
MAX II Device Handbook
Fast I/O connection
to IOE (1)
DirectLink
interconnect from
adjacent LAB
or IOE
DirectLink
interconnect to
adjacent LAB
or IOE
Figure
2–3:
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect,
a look-up table (LUT) chain, and register chain connection lines. There are 26 possible
unique inputs into an LAB, with an additional 10 local feedback input lines fed by LE
outputs in the same LAB. The local interconnect transfers signals between LEs in the
same LAB. LUT chain connections transfer the output of one LE’s LUT to the adjacent
LE for fast sequential LUT connections within the same LAB. Register chain
connections transfer the output of one LE’s register to the adjacent LE’s register
within an LAB. The Quartus
adjacent LABs, allowing the use of local, LUT chain, and register chain connections
for performance and area efficiency.
The LAB local interconnect can drive LEs within the same LAB. The LAB local
interconnect is driven by column and row interconnects and LE outputs within the
same LAB. Neighboring LABs, from the left and right, can also drive an LAB’s local
interconnect through the DirectLink connection. The DirectLink connection feature
minimizes the use of row and column interconnects, providing higher performance
and flexibility. Each LE can drive 30 other LEs through fast local and DirectLink
interconnects.
Logic Element
Figure 2–4
LE0
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LAB
shows the DirectLink connection.
®
II software places associated logic within an LAB or
Figure 2–3
Local Interconnect
Row Interconnect
shows the MAX II LAB.
© October 2008 Altera Corporation
Chapter 2: MAX II Architecture
Column Interconnect
Fast I/O connection
to IOE (1)
DirectLink
interconnect from
adjacent LAB
or IOE
DirectLink
interconnect to
adjacent LAB
or IOE
Logic Array Blocks