EPM7128AETC100-10N Altera, EPM7128AETC100-10N Datasheet - Page 33
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EPM7128AETC100-10N
Manufacturer Part Number
EPM7128AETC100-10N
Description
IC MAX 7000 CPLD 128 100-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7128AETC100-10N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Cpld Type
EEPROM
No. Of Macrocells
128
No. Of I/o's
84
Propagation Delay
10ns
Global Clock Setup Time
6.6ns
Frequency
98MHz
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2027
EPM7128AETC100-10N
EPM7128AETC100-10N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7128AETC100-10N
Manufacturer:
ALTERA
Quantity:
1 920
Company:
Part Number:
EPM7128AETC100-10N
Manufacturer:
ALTERA74
Quantity:
350
Part Number:
EPM7128AETC100-10N
Manufacturer:
ALTERA
Quantity:
20 000
Altera Corporation
Figure 12. MAX 7000A Switching Waveforms
t
driven at 3 V for a logic
high and 0 V for a logic
low. All timing
characteristics are
measured at 1.5 V.
R
& t
F
< 2 ns. Inputs are
(Logic Array Output)
Parallel Expander
Shared Expander
Register Output
Input or I/O Pin
Register to PIA
Data or Enable
Clock into PIA
to Logic Array
Global Clock
Logic Array
Logic Array
Logic Array
Logic Array
Output Pin
at Register
PIA Delay
Clock into
Data from
Clock Pin
Input Pin
Register
Clock at
I/O Pin
Output
Global
Delay
Delay
to Pin
Input
Combinatorial Mode
Global Clock Mode
Array Clock Mode
t
t
R
R
t
t
IN
t
t
SU
IN
IO
t
MAX 7000A Programmable Logic Device Data Sheet
t
ACH
CH
t
t
H
t
t
t
GLOB
PIA
IN
IO
t
RD
t
t
IC
SU
t
PIA
t
t
ACL
t
CL
SEXP
t
H
t
PIA
t
OD
t
LAC
, t
LAD
t
PEXP
t
t
F
F
t
COMB
t
CLR
, t
PRE
t
OD
t
OD
t
PIA
33