EPM7128AETC100-10N Altera, EPM7128AETC100-10N Datasheet - Page 50
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EPM7128AETC100-10N
Manufacturer Part Number
EPM7128AETC100-10N
Description
IC MAX 7000 CPLD 128 100-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7128AETC100-10N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Cpld Type
EEPROM
No. Of Macrocells
128
No. Of I/o's
84
Propagation Delay
10ns
Global Clock Setup Time
6.6ns
Frequency
98MHz
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2027
EPM7128AETC100-10N
EPM7128AETC100-10N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7128AETC100-10N
Manufacturer:
ALTERA
Quantity:
1 920
Company:
Part Number:
EPM7128AETC100-10N
Manufacturer:
ALTERA74
Quantity:
350
Part Number:
EPM7128AETC100-10N
Manufacturer:
ALTERA
Quantity:
20 000
MAX 7000A Programmable Logic Device Data Sheet
50
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
Table 28. EPM7128A Internal Timing Parameters (Part 1 of 2)
Input pad and buffer delay
I/O input pad and buffer
delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable
delay
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = on
V
Output buffer enable
delay, slow slew rate = off
V
Output buffer enable
delay, slow slew rate = off
V
Output buffer enable
delay, slow slew rate = on
V
Output buffer disable
delay
Register setup time
Register hold time
Register setup time of fast
input
Register hold time of fast
input
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V
= 3.3 V
Parameter
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
C1 = 5 pF
Conditions
Min
1.9
1.5
0.8
1.7
-6
Max
2.4
0.6
0.6
2.7
2.5
0.7
2.4
0.0
0.4
0.9
5.4
4.0
4.5
9.0
4.0
Min
2.4
2.2
1.1
1.9
-7
Note (1)
Speed Grade
Max
0.7
0.7
3.1
3.2
0.8
3.0
3.0
0.0
0.6
1.1
5.6
4.0
4.5
9.0
4.0
Min
3.1
3.3
1.1
1.9
-10
Max
10.0
0.9
0.9
3.6
4.3
1.1
4.1
4.1
0.0
0.7
1.2
5.7
5.0
5.5
5.0
Altera Corporation
Min
3.8
4.3
1.1
1.9
-12
Max
10.0
1.1
1.1
3.9
5.1
1.3
4.9
4.9
0.0
0.9
1.4
5.9
5.0
5.5
5.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns