EPM570T100C3N Altera, EPM570T100C3N Datasheet

IC MAX II CPLD 570 LE 100-TQFP

EPM570T100C3N

Manufacturer Part Number
EPM570T100C3N
Description
IC MAX II CPLD 570 LE 100-TQFP
Manufacturer
Altera
Series
MAX® IIr
Datasheets

Specifications of EPM570T100C3N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
76
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
570
Family Name
MAX II
# Macrocells
440
Frequency (max)
3.01205GHz
Propagation Delay Time
5.4ns
Number Of Logic Blocks/elements
57
# I/os (max)
76
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1315
EPM570T100C3N

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Introduction
Features
© August 2009 Altera Corporation
MII51001-1.9
The MAX
6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128
to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices
offer high I/O counts, fast performance, and reliable fitting versus other CPLD
architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and
enhanced in-system programmability (ISP), MAX II devices are designed to reduce
cost and power while providing programmable solutions for applications such as bus
bridging, I/O expansion, power-on reset (POR) and sequencing control, and device
configuration control.
The MAX II CPLD has the following features:
Low-cost, low-power CPLD
Instant-on, non-volatile architecture
Standby current as low as 25 µA
Provides fast propagation delay and clock-to-output times
Provides four global clocks with two clocks available per logic array block (LAB)
UFM block up to 8 Kbits for non-volatile storage
MultiVolt core enabling external supply voltages to the device of either
3.3 V/2.5 V or 1.8 V
MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
Bus-friendly architecture including programmable slew rate, drive strength,
bus-hold, and programmable pull-up resistors
Schmitt triggers enabling noise tolerant inputs (programmable per pin)
I/Os are fully compliant with the Peripheral Component Interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V
operation at 66 MHz
Supports hot-socketing
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry
compliant with IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
®
II family of instant-on, non-volatile CPLDs is based on a 0.18-µm,
1. Introduction
MAX II Device Handbook

Related parts for EPM570T100C3N

EPM570T100C3N Summary of contents

Page 1

... Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz Supports hot-socketing ■ Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry ■ compliant with IEEE Std. 1149.1-1990 ■ ISP circuitry compliant with IEEE Std. 1532 © August 2009 Altera Corporation 1. Introduction MAX II Device Handbook ...

Page 2

... MAX II Logic Element to DC and Switching –6 –7 –8 — — — — — — — — — — — — © August 2009 Altera Corporation ...

Page 3

... Micro FineLine FineLine Package BGA BGA Pitch (mm) 0.5 0.5 Area (mm2 Length × width 5 × × 6 (mm × mm) © August 2009 Altera Corporation II software can automatically cross-reference ® 144-Pin 100-Pin Micro FineLine 100-Pin 144-Pin FineLine BGA TQFP TQFP BGA 80 80 — ...

Page 4

... Updated document with MAX IIZ information. Chapter 1: Introduction Referenced Documents EPM240G EPM570G EPM1270G EPM2210G EPM240Z EPM570Z (1) 1.8 V 1.5 V, 1.8 V, 2.5 V, 3.3 V external supply powers the device core directly. white paper Summary of Changes — — — — © August 2009 Altera Corporation ...

Page 5

... Updated timing numbers in Table 1-1. ■ version 1.3 December 2004, Updated timing numbers in Table 1-1. ■ version 1.2 June 2004, Updated timing numbers in Table 1-1. ■ version 1.1 © August 2009 Altera Corporation Changes Made 1–5 Summary of Changes — — — MAX II Device Handbook ...

Page 6

... MAX II Device Handbook Chapter 1: Introduction Document Revision History © August 2009 Altera Corporation ...

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