EPM570 Altera, EPM570 Datasheet
EPM570
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EPM570 Summary of contents
Page 1
... MAX II devices. This section includes the following chapters: ■ ■ ■ ■ ■ ■ Altera Corporation Section I. MAX II Device Family Data Sheet ® II devices. The chapters contain feature definitions of the internal Chapter 1. Introduction Chapter 2. MAX II Architecture Chapter 3. JTAG & In-System Programmability Chapter 4. Hot Socketing & ...
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... December 2004, v1.2 Added content to Power-Up Characteristics section. Updated Figure 4-5. June 2004, v1.1 Corrected Figure 4-2. 5 December 2004, v1.2 Updated timing tables 5-2, 5-4, 5-12, and tables 15-14 through 5-34. Table 5-31 is new. June 2004, v1.1 Updated timing tables 5-15 through 5-32. 6 March 2004, v1.0 Initial Release. MAX II Device Handbook Chapters 1 through 6. Changes Made Altera Corporation ...
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... I/O expansion, power-on reset (POR) and sequencing control, and device configuration control. The following shows the main sections of the MAX II CPLD Family Data Sheet: Altera Corporation December 2004 Chapter 1. Introduction ® II family of instant-on, non-volatile CPLDs is based on a Section Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1– ...
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... Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz Supports hot-socketing Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 ISP circuitry compliant with IEEE Std. 1532 shows MAX II device features. EPM570 240 570 192 440 240 to 570 8,192 ...
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... EPM570, EPM1270, and EPM2210 devices in the 256-pin FineLine BGA package). Vertical migration means that you can migrate to devices whose dedicated pins and JTAG pins are the same and power pins are subsets or supersets for a given package across device densities ...
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... MAX IIG devices do not have an internal voltage regulator and only accept 1 their VCCINT pins. Contact Altera for availability on these devices. MAX II devices operate internally at 1.8 V. Core Version a.b.c variable 1 1 289 361 19 × 19 shows the external supply EPM240G EPM570G EPM1270G EPM2210G (1) 1.8 V 1.5 V, 1.8 V, 2.5 V, 3.3 V Altera Corporation December 2004 ...
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... The global clock lines can also be used for control signals such as clear, preset, or output enable. Figure 2–1 Altera Corporation December 2004 ® II devices contain a two-dimensional row- and column-based shows a functional block diagram of the MAX II device ...
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... Each MAX II device contains a flash memory block within its floorplan. On the EPM240 device, this block is located on the left side of the device. For the EPM570, EPM1270, and EPM2210 devices, the flash memory block is located on the bottom-left area of the device. The majority of this flash memory storage is partitioned as the dedicated configuration flash memory (CFM) block ...
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... Table 2–1 well as the number of LAB rows and columns adjacent to the flash memory area in the EPM570, EPM1270, and EPM2210 devices. The long LAB rows are full LAB rows that extend from one side of row I/O blocks to the other. The short LAB rows are adjacent to the UFM block; their length is shown as width in LAB columns. Table 2– ...
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... Figure 2–2: (1) The device shown is an EPM570 device. EPM1270 and EPM2210 devices have a similar floorplan with more LABs. For the EPM240 devices, the CFM and UFM block is rotated left 90 degrees covering the left side of the device. Logic Array Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local ...
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... LAB’s local interconnect through the DirectLink connection. The DirectLink connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 30 other LEs through fast local and DirectLink interconnects. Altera Corporation December 2004 shows the MAX II LAB. Row Interconnect LE0 ...
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... MAX II Device Handbook, Volume 1 LE0 LE1 LE2 LE3 LE4 LE5 LE6 LE7 Local LE8 LE9 Logic Element LAB Core Version a.b.c variable DirectLink interconnect from right LAB or IOE output DirectLink interconnect to right Altera Corporation December 2004 ...
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... LE also supports dynamic single bit addition or subtraction mode selectable by an LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and DirectLink interconnects. See Altera Corporation December 2004 interconnect structure drives the LAB local interconnect for TM Figure 2– ...
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... LAB Carry-Out Core Version a.b.c variable Register Bypass Programmable Packed Register Register Select LUT chain routing to next LE Row, column, PRN/ALD and DirectLink D Q routing ADATA ENA CLRN Row, column, and DirectLink routing Local Routing Register chain Register output Feedback Altera Corporation December 2004 ...
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... LE, the LAB carry-in from the previous carry-chain LAB, and the register chain connection are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous Altera Corporation December 2004 for more information on LUT chain and Normal mode Dynamic arithmetic mode Core Version a ...
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... Wide) aclr (LAB Wide) Core Version a.b.c variable Figure 2–7). The aload (LAB Wide) ALD/PRE Row, column, and ADATA Q DirectLink routing D Row, column, and ENA DirectLink routing CLRN Local routing LUT chain connection Register chain output Altera Corporation December 2004 ...
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... LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs. The addnsub LAB-wide signal controls whether the LE acts as an adder or subtractor. Altera Corporation December 2004 2–8, the LAB carry-in signal selects either the carry-in0 or Core Version a.b.c variable MAX II Architecture 2– ...
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... Wide) ena (LAB Wide) aclr (LAB Wide) Register Feedback Carry-Out1 Core Version a.b.c variable aload ALD/PRE Row, column, and Q direct link routing D Row, column, and direct link routing CLRN Local routing LUT chain connection Register chain output Altera Corporation December 2004 ...
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... The final carry-out signal is routed to an LE, where it is fed to local, row, or column interconnects. Altera Corporation December 2004 shows the carry-select circuitry in an LAB for a 10-bit full Core Version a.b.c variable ...
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... LAB row, but they do not extend between LAB rows. 2–14 MAX II Device Handbook, Volume 1 LAB Carry-In Carry-In0 Carry-In1 data1 data2 To top of adjacent LAB Core Version a.b.c variable LUT Sum LUT LUT LUT Carry-Out0 Carry-Out1 Altera Corporation December 2004 ...
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... The DirectLink interconnect allows an LAB to drive into the local interconnect of its left and right neighbors. The DirectLink interconnect provides fast communication between adjacent LABs and/or blocks without using row interconnect resources. Altera Corporation December 2004 DirectLink interconnects between LABs R4 interconnects traversing four LABs to the right or left Core Version a ...
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... This pattern is repeated for every LAB in the LAB row. 2–16 MAX II Device Handbook, Volume 1 Adjacent LAB can Drive onto Another C4 Column Interconnects (1) LAB's R4 Interconnect LAB Primary LAB Neighbor LAB (2) Neighbor Core Version a.b.c variable Figure 2–10 shows R4 R4 Interconnect Driving Right Altera Corporation December 2004 ...
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... LE in the LAB for fast shift registers. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. interconnects. Altera Corporation December 2004 LUT chain interconnects within an LAB Register chain interconnects within an LAB C4 interconnects traversing a distance of four LABs and down direction Figure 2– ...
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... Routing Among LEs in the LAB LE0 LUT Chain Routing to Adjacent LE LE1 Local LE2 Interconnect LE3 LE4 LE5 LE6 LE7 LE8 LE9 shows the C4 interconnect connections from an LAB in a Core Version a.b.c variable Register Chain Routing to Adjacent LE's Register Input Altera Corporation December 2004 ...
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... Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Note to Figure 2–12: (1) Each C4 interconnect can drive either up or down four rows. Altera Corporation December 2004 Note (1) Local Interconnect Core Version a.b.c variable MAX II Architecture C4 Interconnect Drives Local and R4 Interconnects Up to Four Rows ...
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... MAX II device's routing scheme. Destination DirectLink R4 (1) C4 (1) (1) ( Core Version a.b.c variable 2–23. UFM Column Row Fast I/O LE Block IOE IOE ( Figure 2–13. Altera Corporation December 2004 ...
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... LAB column clock buffers shown in Figure LAB clock signals and one LAB clear signal. Other control signal types route from the global clock network into the LAB local interconnect. See “LAB Control Signals” on page 2–6 Altera Corporation December 2004 GCLK0 GCLK1 GCLK2 ...
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... LAB column clocks in I/O block regions provide high fan-out output enable signals. (2) LAB column clocks drive to the UFM block. 2–22 MAX II Device Handbook, Volume 1 Note ( UFM Block (2) CFM Block Core Version a.b.c variable LAB Column clock[3.. I/O Block Region Altera Corporation December 2004 ...
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... OSC_ENA ARCLK ARSHFT ARDin DRDin DRCLK DRSHFT Altera Corporation December 2004 Non-volatile storage up to 16-bit wide and 8,192 total bits Two sectors for partitioned sector erase Built-in internal oscillator that optionally drives logic array Program, erase, and busy signals Auto-increment addressing ...
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... Each device stores up to 8,192 bits of data in the UFM block. shows the data size, sector, and address sizes for the UFM block. Table 2–3. UFM Array Size EPM240 EPM570 EPM1270 EPM2210 There are 512 locations with 9-bit addressing ranging from 000h to 1FFh. ...
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... CFM block as shown in EPM240 device is located on the left side of the device adjacent to the left most LAB column. The UFM block for the EPM570, EPM1270, and EPM2210 devices is located on the bottom left portion of the device. The UFM input and output signals interface to all types of interconnects (R4 interconnect, C4 interconnect, and DirectLink interconnect to/from adjacent LAB rows) ...
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... The UFM block inputs and outputs can drive to/from all types of interconnects, not only DirectLink interconnects from adjacent row LABs. 2–26 MAX II Device Handbook, Volume 1 Note (1) CFM Block UFM Block PROGRAM ERASE OSC_ENA RTP_BUSY DRDin DRCLK DRSHFT ARin ARCLK ARSHFT DRDout OSC BUSY Core Version a.b.c variable LAB LAB LAB Altera Corporation December 2004 ...
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... Figure 2–17. EPM570, EPM1270 & EPM2210 UFM Block LAB Row Interface MultiVolt Core The MAX II architecture supports the MultiVolt allows MAX II devices to support multiple V supply. An internal linear voltage regulator provides the necessary 1.8-V internal voltage supply to the device. The voltage regulator supports 3 ...
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... Bus-hold circuitry Programmable pull-up resistors in user mode Unique output enable per pin Open-drain outputs Schmitt trigger inputs Fast I/O connection Programmable input delay Core Version a.b.c variable 1.8-V Core Voltage MAX II Device With "G" Ordering Code Figure 2–19 shows Altera Corporation December 2004 ...
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... The IOEs are located in I/O blocks around the periphery of the MAX II device. There are up to seven IOEs per row I/O block (5 maximum in the EPM240 device) and up to four IOEs per column I/O block. Each column or row I/O block interfaces with its adjacent LAB and MultiTrack Altera Corporation December 2004 Figures DEV_OE ...
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... C4 Interconnects I/O Block Local Interconnect data_in[6..0] Direct Link Interconnect from Adjacent LAB LAB Column clock [3..0] shows how a column I/O block connects to the logic array. Core Version a.b.c variable data_out [6.. [6..0] 7 Row fast_out I/O Block [6.. Row I/O Block Contains up to Seven IOEs Altera Corporation December 2004 ...
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... Local Interconnect R4 Interconnects LAB LAB Local Interconnect C4 Interconnects Note to Figure 2–21: (1) Each of the four IOEs in the column I/O block can have one data_out or fast_out output, one OE output, and one data_in input. Altera Corporation December 2004 Note (1) Column I/O Block OE fast_out [3..0] [3.. Fast I/O Interconnect ...
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... Table 2–4 Table 2–4. MAX II I/O Standards 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI Note to (1) The EPM240 and EPM570 devices support two I/O banks, as shown in Figure standards shown in and banks. 2–32 MAX II Device Handbook, Volume 1 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI describes the I/O standards supported by MAX II devices. ...
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... Figure 2–22. MAX II I/O Banks for EPM240 & EPM570 I/O Bank 1 Notes to Figure 2–22: (1) Figure 2– top view of the silicon die. (2) Figure 2– graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations. The EPM1270 and EPM2210 devices support four I/O banks, as shown in ...
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... For example, when V Table 2–4 on page 2–32 setting for Bank 1. CCIO Core Version a.b.c variable (2) Also Supports the 3.3-V PCI I/O Standard I/O Bank 3 is 3.3 V, Bank 3 CCIO powers both the CCIO except for PCI. These pins Altera Corporation December 2004 ...
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... The output enable signal can originate from the GCLK[3..0] global signals or from the MultiTrack interconnect. The MultiTrack interconnect routes output enable signals and allows for a unique output enable for each output or bidirectional pin. Altera Corporation December 2004 Device EPM1270 ...
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... V where the V maximum is specified by the I/O standard. For 2.5-V OL LVTTL/LVCMOS, the I condition 0.7 V. OUT Core Version a.b.c variable Note (1) Current Strength Setting (mA OUT maximum, OUT OL = 1.7 V and the I condition is OUT OL Altera Corporation December 2004 ...
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... The designer can select this feature individually for each I/O pin. The bus-hold output will drive no higher than V overdriving signals. If the bus-hold feature is enabled, the device cannot use the programmable pull-up option. Altera Corporation December 2004 Core Version a.b.c variable MAX II Device Handbook, Volume 1 ...
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... MAX II Device Handbook, Volume 1 CCIO The programmable pull-up resistor feature should not be used at the same time as the bus-hold feature on a given I/O pin. Core Version a.b.c variable voltage level driven through level of the output CCIO Altera Corporation December 2004 ...
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... MAX II device can drive a device with 5.0-V TTL inputs but not 5.0-V CMOS inputs. In the CCIO case of 5.0-V CMOS, open-drain setting with internal PCI clamp diode (available only on EPM1270 and EPM2210 devices) and external resistor is required. Altera Corporation December 2004 Table 2–7 summarizes MAX II MultiVolt I/O support. ...
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... I/O Structure 2–40 MAX II Device Handbook, Volume 1 Core Version a.b.c variable Altera Corporation December 2004 ...
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... EXTEST 00 0000 1111 BYPASS 11 1111 1111 USERCODE 00 0000 0111 IDCODE 00 0000 0110 Altera Corporation December 2004 Chapter 3. JTAG & In-System ® II devices provide Joint Test Action Group (JTAG) boundary- and all V banks have been fully powered and a CCINT CCIO amount of time has passed. MAX II devices can also use the JTAG ...
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... HIGHZ, CLAMP, and EXTEST instructions do not disable weak pull-up resistors or bus hold features. (2) These instructions are shown in the 1532 BSDL files, which will be posted on the Altera www.altera.com when they are available. 3–2 MAX II Device Handbook, Volume 1 Places the 1-bit bypass register between the TDI and TDO ...
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... Table 3–2. MAX II Boundary-Scan Register Length EPM240 EPM570 EPM1270 EPM2210 Table 3–3. 32-Bit MAX II Device IDCODE Device Version (4 Bits) EPM240 0000 0010 0000 1010 0001 EPM570 0000 0010 0000 1010 0010 EPM1270 0000 0010 0000 1010 0011 EPM2210 0000 0010 0000 1010 0100 Notes to Table 3–2: (1) The most significant bit (MSB the left ...
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... MAX II Device Handbook, Volume 1 Figure 3–1 MAX II Device TDO_U TDI TDI_U TMS_U TCK_U SHIFT_U CLKDR_U UPDATE_U RUNIDLE_U USER1_U Core Version a.b.c variable shows MAX II being used as a DQ[7..0] A[20.. RY/BY General- Purpose Flash Loader Logic (1), (2) Altera Corporation December 2004 ...
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... JTAG chain. The MAX II 1532 BSDL files will be released on the Altera web site when available. Jam Standard Test & Programming Language (STAPL) The Jam STAPL JEDEC standard, JESD71, can be used to program MAX II devices with in-circuit testers, PCs, or embedded processors ...
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... This process is repeated for each CFM and UFM address. Exit ISP – An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. Core Version a.b.c variable II software, or the ® Altera Corporation December 2004 ...
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... For TCK frequencies of 10 MHz, the erase and programming takes less than two seconds for EPM240 and EPM570 devices. Erase and programming times are less than three seconds for EPM1270 and less than four seconds for the EPM2210 devices. The TCK frequency can operate MHz in MAX II devices providing slight improvements in these ISP times ...
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... MAX II devices can be programmed by downloading the information via in-circuit testers, embedded processors, the Altera MasterBlaster™, ByteBlaster™ II, and USB-Blaster cables, and through the universal serial bus (USB)-based Altera Programming Unit (APU) with the appropriate adapter. BP Microsystems, System General, and other programming hardware manufacturers provide programming support for Altera devices ...
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... Signals can be driven into the MAX II device I/O pins and GCLK[3..0] pins before or during power-up or power-down without damaging the device. MAX II devices support any power-up or power-down sequence (V CCIO1 Altera Corporation December 2004 Chapter 4. Hot Socketing & Power-On Reset in MAX II ® II devices offer hot socketing, also known as hot plug-in or hot ...
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... MAX II devices are immune to latch-up when hot socketing. If the TCK JTAG input pin is driven high during hot-socketing, the current on that pin might exceed the specifications above. Core Version a.b.c variable for information about turn-on Power Supplies CCINT and V pins in any CCIO CCINT | < 300 µA. IOPIN Altera Corporation December 2004 ...
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... SRAM logic. The weak pull-up resistor (R) from the I/O pin to V floating. The 3.3-V tolerance control circuit permits the I/O pins to be driven by 3.3 V before V the I/O pins from driving out when the device is not fully powered or Altera Corporation December 2004 Hot Socketing & Power-On Reset in MAX II Devices or V CCINT below the threshold voltage ...
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... PAD VPAD IOE Signal or the Larger of VCCIO or VPAD well 4–3) shows the ESD current discharge path during a positive ESD Core Version a.b.c variable Ensures 3.3-V Tolerance & Hot-Socket The Larger of VCCIO or VPAD Protection VCCIO substrate Altera Corporation December 2004 ...
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... When the I/O pin receives a negative ESD zap at the pin that is less than -0 the voltage drop across a diode), the intrinsic P-Substrate/N+ drain diode is forward biased. Hence, the discharge ESD current path is from GND to the I/O pin, as shown in Altera Corporation December 2004 Hot Socketing & Power-On Reset in MAX II Devices Source ...
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... NMOS Source GND CCINT and begins SRAM download at a maximum voltage of 1 Core Version a.b.c variable I GND and V voltage levels CCINT CCIO voltage level to detect CCINT voltage sag below the MAX II levels are not CCIO CONFIG Altera Corporation December 2004 in ...
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... V for MAX II G devices), the SRAM download restarts and the device begins to operate after t Figure 4–5 during power-up into user mode and from user mode to power-down or brown-out. Altera Corporation December 2004 Hot Socketing & Power-On Reset in MAX II Devices is powered more than t CCIO ) voltage level to detect a brown-out condition ...
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... To hold the tri-states beyond the power-up configuration time, use the DEV_OE pin option. Core Version a.b.c variable (1), (2) Device Resets the SRAM and Tri-States I/O Pins Tri-State Device Resets the SRAM and Tri-States I/O Pins Tri-State profile shown. If not, t stretches CONFIG Altera Corporation December 2004 ...
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... Junction temperature J Notes to Table 5–1: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Conditions beyond those listed in operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Maximum V for MAX II devices is 4.6 V. For MAX IIG devices 2.4 V. ...
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... I V Output voltage O 5–2 MAX II Device Handbook, Volume 1 shows the MAX II device family recommended operating Conditions Minimum 3.00 2.375 1.71 3.00 2.375 1.71 1.425 –0.5 (2), (3), (4) 0 Core Version a.b.c variable Maximum Unit 3.60 V 2.625 V 1.89 V 3.60 V 2.625 V 1.89 V 1.575 V 4 CCIO Altera Corporation December 2004 ...
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... Table 5–3 specifications. Table 5–3. MAX II Device Programming/Erasure Specifications Parameter Erase and reprogram cycles : Note to Table 5–3 (1) This specification applies to the user flash memory (UFM) and CFM blocks. Altera Corporation December 2004 Conditions Minimum For commercial 0 use For industrial –40 use ...
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... CCIO 1.5 V (5) CCIO = 3.3 or 2.5 V, and V = 1.5 V, 1 3.3 V. CCINT CCIO Core Version a.b.c variable Typical Maximum Unit 10 µA 10 µ 460 mV 170 kΩ 40 kΩ 60 kΩ 95 kΩ CCIO . CCIO Altera Corporation December 2004 ...
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... V Low-level output OL voltage Table 5–7. 2.5-V I/O Specifications (Part Symbol Parameter V I/O supply CCIO voltage V High-level input IH voltage V Low-level input IL voltage Altera Corporation December 2004 through 5–10 show the MAX II device family I/O standard Conditions Minimum 3.0 1.7 –0.5 2 –4 mA ( Conditions Minimum 3 ...
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... V CCIO –0.3 0.75 × –2 mA CCIO OH ( Core Version a.b.c variable Maximum Unit 0.2 V 0.4 V 0.7 V Maximum Unit 1.89 V 2.25 V 0.35 × CCIO V 0.45 V Maximum Unit 1.575 0.3 V CCIO 0.35 × CCIO V 0.25 × CCIO Altera Corporation December 2004 ...
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... High sustaining V < V (minimum current Low overdrive 0 V < V < current High overdrive 0 V < V < current Altera Corporation December 2004 Conditions Minimum Typical 3.0 0.5 × V CCIO –0.5 = –500 µA 0.9 × V CCIO = 1.5 mA shows the MAX II device family bus hold specifications. V 1.5 V 1.8 V ...
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... MAX II Device Handbook, Volume 1 shows the power-up timing characteristics for MAX II devices. Note (1) Device Min Typ EPM240 EPM570 EPM1270 EPM2210 web power calculator to estimate the device ® Core Version a.b.c variable Max Unit 200 µs 300 µ ...
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... Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. Altera Corporation December 2004 t R4 ...
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... Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worst- case voltage and junction temperature conditions. Table 5–13. MAX II Device Timing Model Status EPM240 EPM570 EPM1270 EPM2210 Performance Table 5–14 designs. All performance values were obtained with the Quartus II software compilation of megafunctions ...
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... LUT LUT delay t LE register clear CLR delay t LE register preset PRE delay t LE register setup SU time before clock t LE register hold time H after clock Altera Corporation December 2004 Resources Used UFM -3 Speed LEs Blocks Grade 9.8 (3) ( Tables 5–15 ...
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... I/O Standards, drive strengths, XZ for t delay adders associated with different I/O Standards, drive strengths, ZX Core Version a.b.c variable -5 Speed Grade Unit Min Max 388 ps 272 ps 1,400 ps -5 Speed Grade Unit Min Max 261 ps 1,132 ps 2,540 ps 679 ps 274 ps 1,702 ps 1,209 ps 1,604 ps Table 5–16 Altera Corporation December 2004 ...
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... Table 5–18. t IOE MIcroparameter Adders for Slow Slew Rate ZX Standard 3.3-V LVCMOS 3.3-V LVTTL 2.5-V LVTTL 3.3-V PCI 20 mA Altera Corporation December 2004 and 5–18 show the adder delays for t -3 Speed Grade -4 Speed Grade Min Max Min ...
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... Speed Grade Max Min Max –20 –247 –67 –294 –20 –247 –67 –294 –4 –231 –38 –265 –65 –292 Altera Corporation December 2004 Unit Unit ...
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... Maximum delay PB between program rising edge to UFM busy signal rising edge t Minimum delay BP allowed from UFM busy signal going low to program signal going low Altera Corporation December 2004 -3 Speed Grade -4 Speed Grade Min Max Min Max ...
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... Core Version a.b.c variable -5 Speed Grade Unit Min Max 100 µ 960 500 136 350 ns 350 ns Table 5–21. Altera Corporation December 2004 ...
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... Erase Busy Figure 5–3. UFM Program Waveforms 9 Address Bits ARShft t t ASU ACLK ARClk ARDin t ADS DRShft DRClk DRDin DRDout OSC_ENA Program Erase Busy Altera Corporation December 2004 9 Address Bits ADH 16 Data Bits t DCLK t DSS t DCO ADH 16 Data Bits t t ...
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... ACLK ASU ARClk t ADS Erase Busy -4 Speed Grade Max Min Max 369 480 456 593 342 445 through 5–31. Core Version a.b.c variable ADH t OSCS t OSCH EPMX -5 Speed Grade Unit Min Max 591 ps 730 ps 548 ps Altera Corporation December 2004 ...
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... Table 5–23 (1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input pin maximum frequency. Altera Corporation December 2004 shows the external I/O timing parameters for EPM240 -3 Speed Grade -4 Speed Grade ...
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... Timing Model & Specifications Table 5–24 devices. Table 5–24. EPM570 Global Clock External I/O Timing Parameters Symbol Parameter Condition t Worst case PD1 pin to pin delay through 1 look-up table (LUT) t Best case pin PD2 to pin delay through 1 LUT t Global clock SU setup time t Global clock ...
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... Table 5–25 (1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input pin maximum frequency. Altera Corporation December 2004 shows the external I/O timing parameters for EPM1270 -3 Speed Grade -4 Speed Grade ...
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... I/O timing parameters for EPM2210 -3 Speed Grade -4 Speed Grade Min Max Min 3.7 1.4 1.8 0.0 0 2.0 4.7 2.0 170 221 170 221 3.3 4.0 304.0 (1) Core Version a.b.c variable -5 Speed Grade Unit Max Min Max 9.2 11.3 ns 4.8 6.0 ns 2.2 ns 0.0 ns 6.1 2.0 7.5 ns 272 ps 272 ps 4.9 ns 249.9 202.9 MHz Altera Corporation December 2004 ...
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... Trigger With Schmitt Trigger 1.8-V LVTTL Without Schmitt Trigger 1.5-V LVTTL Without Schmitt Trigger 3.3-V PCI Without Schmitt Trigger Altera Corporation December 2004 through 5–31 show the adder delays associated with I/O pins timing parameters shown in SU through 5–26. -3 Speed Grade -4 Speed Grade Min Max ...
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... Speed Grade Max Min Max 104 104 158 195 251 309 738 909 850 1,046 1,694 1,867 4 5 Altera Corporation December 2004 Unit Unit ...
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... LVCMOS Without Schmitt Trigger With Schmitt Trigger 2.5-V LVTTL Without Schmitt Trigger With Schmitt Trigger 2.5-V LVCMOS Without Schmitt Trigger With Schmitt Trigger Altera Corporation December 2004 Adders for Slow Slew Rate OD -3 Speed Grade -4 Speed Grade Min Max Min 5,710 5,391 6,445 ...
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... Core Version a.b.c variable -5 Speed Grade Unit 200 MHz 200 MHz 150 MHz 304 MHz Unit 304 MHz 304 MHz 220 MHz 220 MHz 200 MHz 200 MHz 150 MHz 304 MHz Altera Corporation December 2004 ...
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... CCIO1 t TCK clock high time JCH t TCK clock low time JCL t JTAG port setup time JPSU (2) t JTAG port hold time JPH Altera Corporation December 2004 shows the timing waveforms for the JTAG signals. TMS TDI t JCP t t JCH JCL TCK t t ...
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... This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the t values at 35 ns. 5–28 MAX II Device Handbook, Volume 1 Min ( minimum and t JPSU Core Version a.b.c variable Max Unit and t are maximum JPCO JPZX JPXZ Altera Corporation December 2004 ...
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... Solaris, Linux Red Hat v8.0, and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the NativeLink Device Pin-Outs Printed device pin-outs for MAX II devices will be released on the Altera web site (www.altera.com) and in the MAX II Device Handbook when they are available. Ordering Figure 6– ...
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... Thin quad flat pack (TQFP) ® F: FineLine BGA Dual Marking On MAX II devices, packages display a dual marking for the -4 commercial and -5 industrial ordering codes. For example, both EPM570GT100C4 and EPM570GT100I5 ordering codes are marked on the same package. 6–2 MAX II Device Handbook, Volume 1 240 G T ...