EPM570 Altera, EPM570 Datasheet - Page 85

• Manufacturer Part Number: EPM570
• Description: MAX II Device Family
• Manufacturer: Altera

Altera Corporation
December 2004
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
3.3-V PCI
Table 5–27. External Timing Input Delay Adders
Standard
Without Schmitt
Trigger
With Schmitt
Trigger
Without Schmitt
Trigger
With Schmitt
Trigger
Without Schmitt
Trigger
With Schmitt
Trigger
Without Schmitt
Trigger
Without Schmitt
Trigger
Without Schmitt
Trigger
External Timing I/O Delay Adders
I/O delay timing parameters for I/O standard input and output adders
and input delays are specified by speed grade independent of device
density.
Tables 5–27
for all packages. If an I/O standard is selected other than LVTTL with a
unit value of 16 mA and a fast slew rate, add the selected input delay
adder to the external t
5–26. Add the output delay adder to the external t
Tables 5–23
-3 Speed Grade
Min
Core Version a.b.c variable
through
through 5–26.
Max
334
334
339
291
681
23
0
0
0
5–31
SU
timing parameters shown in
show the adder delays associated with I/O pins
-4 Speed Grade
Min
Max
434
434
441
378
885
30
0
0
0
MAX II Device Handbook, Volume 1
DC & Switching Characteristics
-5 Speed Grade
Min
CO
Tables 5–23
and t
1,090
Max
535
535
543
466
37
PD
0
0
0
shown in
through
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
5–23