EPM570 Altera, EPM570 Datasheet - Page 21

• Manufacturer Part Number: EPM570
• Description: MAX II Device Family
• Manufacturer: Altera

MultiTrack
Interconnect
Altera Corporation
December 2004
Clear & Preset Logic Control
LAB-wide signals control the logic for the register’s clear and preset
signals. The LE directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not require a
NOT-gate push-back technique. MAX II devices support simultaneous
preset/asynchronous load and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each
LAB supports up to two clears and one preset signal.
In addition to the clear and preset ports, MAX II devices provide a chip-
wide reset pin (DEV_CLRn) that resets all registers in the device. An
option set before compilation in the Quartus II software controls this pin.
This chip-wide reset overrides all other control signals and uses its own
dedicated routing resources (i.e., it does not use any of the four global
resources). Driving this signal low before or during power-up prevents
user mode from releasing clears within the design. This allows you to
control when clear is released on a device that has just been powered-up.
If not set for its chip-wide reset function, the DEV_CLRn pin is a regular
I/O pin.
Upon power-up, each register in a MAX II device may be set to either a
high or low state. This power-up state is specified at design entry. By
default, all registers are set to power up low.
In the MAX II architecture, connections between LEs, the UFM, and
device I/O pins are provided by the MultiTrack interconnect structure.
The MultiTrack interconnect consists of continuous, performance-
optimized routing lines used for inter- and intra-design block
connectivity. The Quartus II Compiler automatically places critical design
paths on faster interconnects to improve design performance.
The MultiTrack interconnect consists of row and column interconnects
that span fixed distances. A routing structure with fixed length resources
for all devices allows predictable and short delays between logic levels
instead of large delays associated with global or long routing lines.
Dedicated row interconnects route signals to and from LABs within the
same row. These row resources include:
■
■
The DirectLink interconnect allows an LAB to drive into the local
interconnect of its left and right neighbors. The DirectLink interconnect
provides fast communication between adjacent LABs and/or blocks
without using row interconnect resources.
DirectLink interconnects between LABs
R4 interconnects traversing four LABs to the right or left
Core Version a.b.c variable
MAX II Device Handbook, Volume 1
MAX II Architecture
2–15