EPM7128SQC160-15N Altera, EPM7128SQC160-15N Datasheet - Page 10

• Manufacturer Part Number: EPM7128SQC160-15N
• Description: IC MAX 7000 CPLD 128 160-PQFP
• Manufacturer: Altera
• Series: MAX® 7000r

Specifications of EPM7128SQC160-15N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 128
• Number Of Gates: 2500
• Number Of I /o: 100
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Voltage: 5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 8
• Cpld Type: EEPROM
• No. Of Macrocells: 128
• No. Of I/o's: 100
• Propagation Delay: 15ns
• Global Clock Setup Time: 11ns
• Frequency: 76.9MHz
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 544-2043; EPM7128SQC160-15N

MAX 7000 Programmable Logic Device Family Data Sheet
Figure 4. MAX 7000E & MAX 7000S Device Macrocell
10
36 Signals
from PIA
Logic Array
Product Terms
16 Expander
Figure 4
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register clear, preset, clock, and clock enable control
functions. Two kinds of expander product terms (“expanders”) are
available to supplement macrocell logic resources:
■
■
The Altera development system automatically optimizes product-term
allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera development software then selects the most efficient flipflop
operation for each registered function to optimize resource utilization.
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
Product-
Select
Matrix
Term
shows a MAX 7000E and MAX 7000S device macrocell.
Shared Logic
Expanders
Parallel Logic
Expanders
(from other
macrocells)
Global
Clear
Select
Clear
Clocks
2
Global
VCC
Enable
Select
Clock/
Fast Input
Select
ENA
D/T
CLRN
PRN
to PIA
Q
Programmable
Register
Altera Corporation
Register
Bypass
from
I/O pin
to I/O
Control
Block