EPM7256EGI192-20 Altera, EPM7256EGI192-20 Datasheet - Page 18

• Manufacturer Part Number: EPM7256EGI192-20
• Description: IC MAX 7000 CPLD 256 192-PGA
• Manufacturer: Altera
• Series: MAX® 7000r

Specifications of EPM7256EGI192-20

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 20.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 5000
• Number Of I /o: 164
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 192-PGA
• Voltage: 5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 16
• Family Name: MAX 7000
• # Macrocells: 256
• Number Of Usable Gates: 5000
• Frequency (max): 83.33MHz
• Propagation Delay Time: 20ns
• Number Of Logic Blocks/elements: 16
• # I/os (max): 164
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 192
• Package Type: CPGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2356

MAX 7000 Programmable Logic Device Family Data Sheet
18
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
■
■
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000S Device
The time required to program a single MAX 7000S device in-system can
be calculated from the following formula:
where: t
The ISP times for a stand-alone verification of a single MAX 7000S device
can be calculated from the following formula:
where: t
t PROG
t
VER
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
=
=
t
VPULSE
t
Cycle
f
t
Cycle
TCK
t PPULSE
PROG
PPULSE
VER
VPULSE
PTCK
VTCK
+
+
Cycle
--------------------------------
Cycle
------------------------------- -
= Programming time
= Sum of the fixed times to erase, program, and
= Number of TCK cycles to program a device
= TCK frequency
f
= Verify time
= Sum of the fixed times to verify the EEPROM cells
= Number of TCK cycles to verify a device
TCK
f
TCK
VTCK
verify the EEPROM cells
PTCK
Altera Corporation