XA9572XL-15VQG64I Xilinx Inc, XA9572XL-15VQG64I Datasheet - Page 9

• Manufacturer Part Number: XA9572XL-15VQG64I
• Description: IC CPLD 3.3V 72MCELL 64-VQFP
• Manufacturer: Xilinx Inc
• Series: XA9500XL XAr

Specifications of XA9572XL-15VQG64I

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 15.5ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 72
• Number Of Gates: 1600
• Number Of I /o: 52
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Features: Automotive
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

7. Do not drive I/Os pins above the V
8. Do not rely on the I/O states before the CPLD
9. Use a voltage regulator which can provide sufficient
10. Ensure external JTAG terminations for TMS, TCK, TDI,
11. Attach all CPLD V
12. Decouple all V
Recommendations
The following recommendations are for all automotive appli-
cations.
1. Use strict synchronous design (only one clocking event)
Warranty Disclaimer
THIS WARRANTY DOES NOT EXTEND TO ANY IMPLEMENTATION IN AN APPLICATION OR ENVIRONMENT THAT IS
NOT CONTAINED WITHIN XILINX SPECIFICATIONS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE
NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS. FURTHER, PRODUCTS ARE NOT WARRANTED
FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF THE VEHICLE UNLESS THERE IS A FAIL-SAFE OR
REDUNDANCY FEATURE AND ALSO A WARNING SIGNAL TO THE OPERATOR OF THE VEHICLE UPON FAILURE.
USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE
LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
Further Reading
The following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing
Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down.
Data Sheets, Application Notes, and White Papers.
DS599 (v1.1) April 3, 2007
Product Specification
includes some I/O driving circuits beyond the input and
output buffers, may have contention with external
pull-down resistors, and, consequently, the I/O will not
switch as expected.
I/O bank.
a. The current flow can go into V
b. It can also increase undesired leakage current
c. If done for too long, it can reduce the life of the
configures.
current during device power up. As a rule of thumb, the
regulator needs to provide at least three times the peak
current while powering up a CPLD in order to guarantee
the CPLD can configure successfully.
TDO comply with IEEE 1149.1. All Xilinx CPLDs have
internal weak pull-ups of ~50 kΩ on TDI, TMS, and
TCK.
necessary power and ground supplies around the
CPLD.
0.01 μF and 0.1 μF closest to the pins for each
V
if possible. A synchronous system is more robust than
an asynchronous one.
CC
voltage regulator.
associated with the device.
device.
/V
CCIO
R
-GND pair.
CC
and V
CC
and GND pins in order to have
CCIO
pins with capacitors of
CCIO
CCIO
and affect a user
assigned to its
www.xilinx.com
2. Include JTAG stakes on the PCB. JTAG stakes can be
3. XA9500XL Automotive CPLDs work with any power
4. Do not disregard report file warnings. Software
5. Understand the Timing Report. This report file provides
6. Review Fitter Report equations. Equations can be
7. Let design software define pinouts if possible. Xilinx
8. Perform a post-fit simulation for all speeds to identify
9. Distribute SSOs (Simultaneously Switching Outputs)
10. Terminate high speed outputs to eliminate noise caused
used to test the part on the PCB. They add benefit in
reprogramming part on the PCB, inspecting chip
internals with INTEST, identifying stuck pins, and
inspecting programming patterns (if not secured).
sequence, but it is preferable to power the V
(internal V
which any glitches from device I/Os are unwanted.
identifies potential problems when compiling, so the
report file is worth inspecting to see exactly how your
design is mapped onto the logic.
a speed summary along with warnings. Read the timing
file (*.tim) carefully. Analyze key signal chains to
determine limits to given clock(s) based on logic
analysis.
shown in ABEL-like format, or can also be displayed in
Verilog or VHDL formats. The Fitter Report also
includes switch settings that are very informative of
other device behaviors.
CPLD software works best when it selects the I/O pins
and manages resources for users. It can spread signals
around and improve pin-locking. If users must define
pins, plan resources in advance.
any possible problems (such as race conditions) that
might occur when fast-speed silicon is used instead of
slow-speed silicon.
evenly around the CPLD to reduce switching noise.
by very fast rising/falling edges.
CC
) before the V
XA9572XL Automotive CPLD
CCIO
for the applications in
CCI
9