XA2C64A-7VQG100I Xilinx Inc, XA2C64A-7VQG100I Datasheet

IC CPLD 64MCELL 64 I/O 100-VQFP

XA2C64A-7VQG100I

Manufacturer Part Number
XA2C64A-7VQG100I
Description
IC CPLD 64MCELL 64 I/O 100-VQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Datasheet

Specifications of XA2C64A-7VQG100I

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.7ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1500
Number Of I /o
64
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Features
JTAG
Voltage
1.8V
Memory Type
CMOS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-

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DS553 (v1.1) May 5, 2007
Features
DS553 (v1.1) May 5, 2007
Product Specification
© 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
AEC-Q100 device qualification and full PPAP support
available in both I-grade and extended temperature
Q-grade
Guaranteed to meet full electrical specifications over
T
(Q-grade)
Optimized for 1.8V systems
Industry’s best 0.18 micron CMOS CPLD
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-
Available in the following package options
-
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Advanced system features
-
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-
-
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-
-
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-
A
= -40° C to +105° C with T
Optimized architecture for effective logic synthesis
Multi-voltage I/O operation — 1.5V to 3.3V
44-pin VQFP with 33 user I/O
100-pin VQFP with 64 user I/O
Pb-free only for all packages
Fastest in system programming
·
IEEE1149.1 JTAG Boundary Scan Test
Optional Schmitt-trigger input (per pin)
Two separate I/O banks
RealDigital™ 100% CMOS product term
generation
Flexible clocking modes
·
Global signal options with macrocell control
·
·
·
Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
Advanced design security
Optional bus-hold, 3-state or weak pullup on
selected I/O pins
Open-drain output option for Wired-OR and LED
drive
Optional configurable grounds on unused I/Os
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
PLA architecture
·
·
Hot pluggable
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
1.8V ISP using IEEE 1532 (JTAG) interface
Optional DualEDGE triggered registers
Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
Superior pinout retention
100% product term routability across function
block
R
J
Maximum = +125° C
0
0
www.xilinx.com
0
XA2C64A CoolRunner-II
Automotive CPLD
Product Specification
Refer to the CoolRunner™-II Automotive CPLD family data
sheet for architecture description.
Description
The CoolRunner-II Automotive 64-macrocell device is
designed for both high performance and low power applica-
tions. This lends power savings to high-end communication
equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall
system reliability is improved
This device consists of four Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
The CoolRunner-II Automotive 64-macrocell CPLD is I/O
compatible
LVCMOS25, and LVCMOS33 (see
WARNING: Programming temperature range of
T
A
= 0° C to +70° C.
with
standard
LVTTL
Table
and
1). This device is
LVCMOS18,
1

Related parts for XA2C64A-7VQG100I

XA2C64A-7VQG100I Summary of contents

Page 1

... Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS553 (v1.1) May 5, 2007 Product Specification 0 XA2C64A CoolRunner-II Automotive CPLD Product Specification 0 0 Refer to the CoolRunner™ ...

Page 2

... EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. CoolRunner-II Automotive CPLDs are also 1.5V I/O com- patible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XA2C64A IOSTANDARD Attribute LVTTL design technology ...

Page 3

... I I/O High-Z leakage IH Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block) tested at DS553 (v1.1) May 5, 2007 Product Specification XA2C64A CoolRunner-II Automotive CPLD Description (1) (1) Device Packaging information on the Xilinx website. For Pb free Parameter Industrial T = –40°C to +85°C ...

Page 4

... XA2C64A CoolRunner-II Automotive CPLD LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications Symbol Parameter V Input source voltage CCIO V High level input voltage IH V Low level input voltage IL V High level output voltage, OH Industrial grade High level output voltage, Q-grade V Low level output voltage, ...

Page 5

... Low level output voltage, Q-grade Notes: 1. Hysteresis used on 1.5V inputs. Schmitt Trigger Input DC Voltage Specifications Symbol Parameter V Input source voltage CCIO V Input hysteresis threshold voltage DS553 (v1.1) May 5, 2007 Product Specification XA2C64A CoolRunner-II Automotive CPLD Test Conditions - - 0. – CCIO CCIO I = –0.1 mA 1.7V V ...

Page 6

... XA2C64A CoolRunner-II Automotive CPLD AC Electrical Characteristics Over Recommended Operating Conditions Symbol T Propagation delay single p-term PD1 T Propagation delay OR array PD2 T Direct input register clock setup time SUD T Setup time (single p-term) SU1 T Setup time (OR array) SU2 T Direct input register hold time ...

Page 7

... Output slew rate adder SLEW15 I/O Standard Time Adder Delays 1.8V CMOS T Hysteresis input adder HYS18 T Output adder OUT18 T Output slew rate adder SLEW DS553 (v1.1) May 5, 2007 Product Specification XA2C64A CoolRunner-II Automotive CPLD -7 (1) Min. Max. - 2.4 - 4.0 - 2 ...

Page 8

... XA2C64A CoolRunner-II Automotive CPLD Internal Timing Parameters (Continued) Symbol Parameter I/O Standard Time Adder Delays 2.5V CMOS T Standard input adder IN25 T Hysteresis input adder HYS25 T Output adder OUT25 T Output slew rate adder SLEW25 I/O Standard Time Adder Delays 3.3V CMOS/TTL T Standard input adder ...

Page 9

... Number of Outputs Switching Figure 2: Derating Curve for T AC Test Circuit Figure 3: AC Load Circuit DS553 (v1.1) May 5, 2007 Product Specification Typical I/O Output Curves DS092_02_092302 PD www.xilinx.com XA2C64A CoolRunner-II Automotive CPLD Vo Output Volts Figure 4: Typical I/O Output Curves Vdde1 1.5V 1.8V 2.5V 3.3V 9 ...

Page 10

... XA2C64A CoolRunner-II Automotive CPLD Pin Descriptions Function Block 1(GTS1) 1(GTS0) 1(GTS3) 1(GTS2) 1(GSR 2(GCK0) 2(GCK1) 2 2(GCK2 Macrocell VQG44 www.xilinx.com VQG100 I/O Banking 13 Bank 2 12 Bank 2 11 Bank 2 10 Bank 2 9 Bank 2 8 Bank 2 7 Bank 2 6 Bank 2 4 Bank 2 3 Bank 2 ...

Page 11

... XA2C64A CoolRunner-II Automotive CPLD VQG100 I/O Banking 91 Bank 2 90 Bank 2 89 Bank 2 81 Bank 2 79 Bank 2 78 Bank 2 77 Bank 2 76 Bank 2 74 Bank 2 72 Bank 2 71 Bank 2 70 Bank 2 68 Bank 2 67 Bank 2 64 Bank 2 61 Bank 2 35 Bank 1 ...

Page 12

... Power bank 1 I CCIO1 Power bank 2 I CCIO2 Ground 10, 23 connects Total user I/O Ordering Information Device Ordering No. Pin/Ball and Part Marking No. Spacing XA2C64A-7VQG44I 0.8mm XA2C64A-8VQG44Q 0.8mm XA2C64A-7VQG100I 0.5mm XA2C64A-8VQG100Q 0.5mm Notes Industrial (T = –40° +85° C Automotive ( A 12 PC44 VQ44 QFG48 ...

Page 13

... I Speed Part marking for non-chip scale package Figure 5: Sample Package with Part Marking I/O (1) 33 I/O (1) 32 I/O (1) 31 I/O (3) 30 I/O 29 I CCIO2 GND 25 TDO 24 I/O 23 www.xilinx.com XA2C64A CoolRunner-II Automotive CPLD This line not related to device part number 13 ...

Page 14

... XA2C64A CoolRunner-II Automotive CPLD 1 (1) I/O 2 (1) I/O 3 (1) I/O 4 (1) I AUX 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O I GND 21 (2) 22 I/O (2) I (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset CoolRunner-II Automotive Requirements and Recommendations ...

Page 15

... USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. DS553 (v1.1) May 5, 2007 Product Specification XA2C64A CoolRunner-II Automotive CPLD internals with INTEST, identifying stuck pins, and inspecting programming patterns (if not secured). 3. CoolRunner-II Automotive CPLDs work with any power ...

Page 16

... XA2C64A CoolRunner-II Automotive CPLD Additional Information Additional information is available for the following CoolRunner-II topics: • XAPP784: Bulletproof CPLD Design Practices • XAPP375: Timing Model • XAPP376: Logic Engine • XAPP378: Advanced Features • XAPP382: I/O Characteristics • XAPP389: Powering CoolRunner-II • ...

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