ATF1502AS-10AC44 Atmel, ATF1502AS-10AC44 Datasheet - Page 12

• Manufacturer Part Number: ATF1502AS-10AC44
• Description: IC CPLD 32 MACROCELL 10NS 44TQFP
• Manufacturer: Atmel
• Series: ATF1502AS(L)r

Specifications of ATF1502AS-10AC44

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Macrocells: 32
• Number Of I /o: 32
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Voltage: 4.75 V ~ 5.25 V
• Memory Type: EEPROM
• Circuit Type: Electrically Erasable
• Logic Function: Programmable
• Logic Type: CPLD
• Package Type: TQFP-44
• Special Features: Security Fuse
• Temperature, Operating, Range: 0 to +70 °C
• Voltage, Supply: 5.25 V
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device
• Other names: ATF1502AS-10AC

Power-down
Mode
Power-down AC Characteristics
Notes:
Absolute Maximum Ratings*
12
Symbol
t
t
t
t
t
t
t
t
t
t
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
IVDH
GVDH
CVDH
DHIX
DHGX
DHCX
DLIV
DLGV
DLCV
DLOV
1. For slow slew outputs, add t
2. Pin or product term.
ATF1502AS(L)
Parameter
Valid I, I/O before PD High
Valid OE
Valid Clock
I, I/O Don’t Care after PD High
OE
Clock
PD Low to Valid I, I/O
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
(2)
(2)
Don’t Care after PD High
Don’t Care after PD High
(2)
(2)
before PD High
before PD High
The ATF1502AS includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply
current is reduced to less than 5 mA. During power-down, all output data and internal logic
states are latched and held. Therefore, all registered and combinatorial output data remain
valid. Any outputs that were in a high-Z state at the onset will remain at high-Z. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold
latches remain active to ensure that pins do not float to indeterminate levels, further reducing
system power. The power-down pin feature is enabled in the logic design file. Designs using
the power-down pin may not use the PD pin logic array input. However, all other PD pin mac-
rocell resources may still be used, including the buried feedback and foldback product term
array inputs.
SSO
.
(1)(2)
(1)
(1)
(1)
Min
7
7
7
*NOTICE:
Note:
-7
Max
12
12
12
1
1
1
1
1. Minimum voltage is -0.6V DC, which may under-
Min
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
which may overshoot to 7.0V for pulses of less
than 20 ns.
10
10
10
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
-10
Max
15
15
15
1
1
1
1
Min
15
15
15
-15
Max
25
25
25
1
1
1
1
Min
25
25
25
CC
-25
+ 0.75V DC,
Max
35
35
35
0995K–PLD–6/05
1
1
1
1
Units
ns
ns
ns
ns
ns
µs
µs
ns
µs
µs