ATF1500AL-20JC Atmel, ATF1500AL-20JC Datasheet - Page 4
![IC CPLD 20NS 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATF1500AL-20JC
Manufacturer Part Number
ATF1500AL-20JC
Description
IC CPLD 20NS 44PLCC
Manufacturer
Atmel
Series
ATF1500A(L)r
Datasheet
1.ATF1500A-10JU.pdf
(19 pages)
Specifications of ATF1500AL-20JC
Programmable Type
In System Programmable (min 100 program/erase cycles)
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Macrocells
32
Number Of I /o
32
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
4.75 V ~ 5.25 V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
ATF1500AL20JC
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ATF1500A(L) Macrocell
ATF1500A Macrocell
The ATF1500A macrocell is flexible enough to support
highly-complex logic functions operating at high speed. The
macrocell consists of five sections: product terms and prod-
uct term select multiplexer, OR/XOR/CASCADE logic, a
flip-flop, output select and enable, and logic array inputs.
Product Terms and Select Mux
Each ATF1500A macrocell has five product terms. Each
product term receives as its inputs all signals from both the
global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is deter-
mined by the design compiler that selects the optimum
macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1500A macrocell’s OR/XOR/CASCADE logic
structure is designed to efficiently support all types of logic.
Within a single macrocell, all the product terms can be
4
ATF1500A(L)
routed to the OR gate, creating a five input AND/OR sum
term. With the addition of the CASIN from neighboring
macrocells, this can be expanded to as many as 40 product
terms with little small additional delay.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato-
rial outputs, the fixed level input allows output polarity
selection. For registered functions, the fixed levels allow De
Morgan minimization of the product terms. The XOR gate is
also used to emulate T-type flip-flops.
Flip-flop
The ATF1500A’s flip-flop has very flexible data and control
functions. The data input can come from either the XOR
gate or from a separate product term. Selecting the sepa-
rate product term allows creation of a buried registered
feedback within a combinatorial output macrocell.