ATF1504AS-10JI68 Atmel, ATF1504AS-10JI68 Datasheet - Page 10
![IC CPLD 10NS 68PLCC](/photos/6/71/67127/453-68-plcc_sml.jpg)
ATF1504AS-10JI68
Manufacturer Part Number
ATF1504AS-10JI68
Description
IC CPLD 10NS 68PLCC
Manufacturer
Atmel
Series
ATF1504AS(L)r
Datasheet
1.ATF1504AS-10JC84.pdf
(33 pages)
Specifications of ATF1504AS-10JI68
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Macrocells
64
Number Of I /o
48
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Voltage
5V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
ATF1504AS10JI68
Available stocks
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Part Number
Manufacturer
Quantity
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Programming
ISP Programming
Protection
10
ATF1504AS(L)
ATF1504AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG
protocol. This capability eliminates package handling normally required for programming
and facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1504AS via
the PC. ISP is performed by using either a download cable or a comparable board tester
or a simple microprocessor interface.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial
Vector Format (SVF) files can be created by Atmel provided software utilities.
ATF1504AS devices can also be programmed using standard third-party programmers.
With third-party programmer, the JTAG ISP port can be disabled thereby allowing
four additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
The ATF1504AS has a special feature that locks the device and prevents the inputs and
I/O from driving if the programming process is interrupted for any reason. The inputs
and I/O default to high-Z state during such a condition. In addition the pin-keeper option
preserves the former state during device programming, if this circuit were previously
programmed on the device. This prevents disturbing the operation of other circuits in the
system while the ATF1504AS is being programmed via ISP.
All ATF1504AS devices are initially shipped in the erased state thereby making them
ready to use for ISP.
Note:
For more information refer to the “Designing for In-System Programmability with Atmel
CPLDs” application note.
0950N–PLD–07/02