XC95288XV-7CS280C Xilinx Inc, XC95288XV-7CS280C Datasheet - Page 6
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XC95288XV-7CS280C
Manufacturer Part Number
XC95288XV-7CS280C
Description
IC CPLD 2.5V ISP 280-CSP
Manufacturer
Xilinx Inc
Series
XC9500XVr
Specifications of XC95288XV-7CS280C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
2.37 V ~ 2.62 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
288
Number Of Gates
6400
Number Of I /o
192
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
280-CSBGA
Voltage
2.5V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Available stocks
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Manufacturer
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XC9500XV Family High-Performance CPLD
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in
originates from either of three global clocks or a product
6
I/O/GCK2
I/O/GCK3
I/O/GCK1
I/O/GSR
Figure
4, the macrocell register clock
Figure 4: Macrocell Clock and Set/Reset Capability
Product Term Set
Product Term Clock
Product Term Reset
Global Set/Reset
Global Clock 1
Global Clock 2
Global Clock 3
www.xilinx.com
term clock. Both true and complement polarities of the
selected clock source can be used within each macrocell. A
GSR input is also provided to allow user registers to be set
to a user-defined state.
DS049 (v3.0) June 25, 2007
D/T
EC
S
R
Product Specification
Macrocell
DS049_04_041400
R