XC9536XV-5CS48C Xilinx Inc, XC9536XV-5CS48C Datasheet - Page 4
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XC9536XV-5CS48C
Manufacturer Part Number
XC9536XV-5CS48C
Description
IC CPLD 2.5V ISP 48-CSP
Manufacturer
Xilinx Inc
Series
XC9500XVr
Specifications of XC9536XV-5CS48C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.0ns
Voltage Supply - Internal
2.37 V ~ 2.62 V
Number Of Logic Elements/blocks
2
Number Of Macrocells
36
Number Of Gates
800
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-CSBGA
Voltage
2.5V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of I /o
-
Number Of Logic Elements/cells
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
XC9500XV Family High-Performance CPLD
Macrocell
Each XC9500XV macrocell may be individually configured
for a combinatorial or registered function. The macrocell
and associated FB logic is shown in
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, clock enable, set/reset, and output enable.
4
Fast CONNECT II
Switch Matrix
From
54
Figure
Programmable
AND-Array
Figure 2: XC9500XV Function Block
3.
www.xilinx.com
Allocators
Product
Term
Set/Reset
The product term allocator associated with each macrocell
selects how the five direct terms are used.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
are initialized to the user-defined preload state (default to 0
if unspecified).
Global
Macrocell 18
1
Macrocell 1
Clocks
Global
3
18
18
18
OUT
To Fast CONNECT II
Switch Matrix
PTOE
DS049 (v3.0) June 25, 2007
Product Specification
To I/O Blocks
DS049_02_041400
R