DSP56303AG100 Freescale Semiconductor, DSP56303AG100 Datasheet - Page 56
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DSP56303AG100
Manufacturer Part Number
DSP56303AG100
Description
IC DSP 24BIT 100MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
DSP563xxr
Type
Fixed Pointr
Datasheet
1.DSP56303AG100.pdf
(108 pages)
Specifications of DSP56303AG100
Interface
Host Interface, SSI, SCI
Clock Rate
100MHz
Non-volatile Memory
ROM (576 B)
On-chip Ram
24kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
144-LQFP
Package
144LQFP
Maximum Speed
100 MHz
Ram Size
24 KB
Device Million Instructions Per Second
100 MIPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSP56303AG100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
DSP56303AG100B1
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
DSP56303AG100R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Specifications
2.5.7
2-36
Notes:
No.
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
Synchronous clock cycle
Clock low period
Clock high period
Output data setup to clock falling edge (internal
clock)
Output data hold after clock rising edge (internal
clock)
Input data setup time before clock rising edge
(internal clock)
Input data not valid before clock rising edge
(internal clock)
Clock falling edge to output data valid (external
clock)
Output data hold after clock rising edge (external
clock)
Input data setup time before clock rising edge
(external clock)
Input data hold time after clock rising edge
(external clock)
Asynchronous clock cycle
Clock low period
Clock high period
Output data setup to clock rising edge (internal
clock)
Output data hold after clock rising edge (internal
clock)
1.
2.
3.
4.
SCI Timing
V
t
t
control register and T
An expression is used to compute the number listed as the minimum or maximum value as appropriate.
SCC
ACC
CC
= 3.3 V ± 0.3 V; T
= synchronous clock cycle time (for internal clock, t
= asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, t
Characteristics
C
J
).
= − 40°C to +100 °C, C
1
DSP56303 Technical Data, Rev. 11
Table 2-17.
L
= 50 pF.
Symbol
t
t
SCC
ACC
2
3
SCC
SCI Timings
is determined by the SCI clock control register and T
t
t
SCC
t
SCC
SCC
t
SCC
/4 + 0.5 × T
/4 + 0.5 × T
Expression
/4 + 0.5 × T
t
t
t
t
t
t
SCC
SCC
ACC
ACC
ACC
ACC
T
/4 − 0.5 × T
64 × T
8 × T
C
/2 − 10.0
/2 − 10.0
/2 − 10.0
/2 − 10.0
/2 − 30.0
/2 − 30.0
+ 8.0
C
C
C
C
C
+ 25.0
− 17.0
− 5.5
C
ACC
is determined by the SCI clock
640.0
310.0
310.0
290.0
290.0
Freescale Semiconductor
Min
53.3
16.7
16.7
15.0
50.0
18.0
8.0
0.0
9.0
—
—
100 MHz
Max
19.5
32.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C
).
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns