ADSP-BF527KBCZ-6C2 Analog Devices Inc, ADSP-BF527KBCZ-6C2 Datasheet - Page 61

• Manufacturer Part Number: ADSP-BF527KBCZ-6C2
• Description: IC DSP 16BIT 600MHZ 289CSPBGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF527KBCZ-6C2

• Package / Case: 289-CSPBGA
• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 600MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.10V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Cache On Chip L1/l2 Memory: 48KB
• Core Frequency Typ: 600MHz
• Dsp Type: Core
• External Supported Memory: SDRAM, SRAM, FLASH, ROM
• Interface Type: SPI, Parallel, 2 Wire
• Rohs Compliant: Yes
• Mmac: 1200
• No. Of Pins: 289
• Package: 289CSP-BGA
• Maximum Speed: 600 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Timer Cycle Timing
Table 52
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
Table 52. Timer Cycle Timing
1
2
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
WL
WH
TIS
TIH
HTO
TOD
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
and
Timer Pulse Width Input
Low (Measured In SCLK
Cycles)
Timer Pulse Width Input
High (Measured In SCLK
Cycles)
Timer Input Setup Time
Before CLKOUT Low
Timer Input Hold Time
After CLKOUT Low
Timer Pulse Width Output
(Measured In SCLK Cycles)
Timer Output Update
Delay After CLKOUT High
SCLK
Figure 31
/2) MHz.
1
1
TMRx OUTPUT
TMRx INPUT
CLKOUT
describe timer expired operations. The
2
2
Min
t
t
10
–2
t
SCLK
SCLK
SCLK
ADSP-BF522/ADSP-BF524/ADSP-BF526
1.8V Nominal
–1.5
V
DDEXT
Max
(2
6
32
– 1)t
Rev. B | Page 61 of 88 | May 2010
t
TIS
SCLK
Figure 31. Timer Cycle Timing
Min
t
t
7
–2
t
SCLK
SCLK
SCLK
2.5/3.3V Nominal
t
WH
– 1
,t
WL
t
TIH
V
DDEXT
Max
(2
6
32
– 1)t
t
TOD
SCLK
Min
t
t
8.1
–2
t
SCLK
SCLK
SCLK
ADSP-BF523/ADSP-BF525/ADSP-BF527
1.8V Nominal
– 1
t
HTO
V
DDEXT
Max
(2
6
32
– 1)t
SCLK
Min
t
t
6.2
–2
t
SCLK
SCLK
SCLK
2.5/3.3V Nominal
– 1
V
DDEXT
Max
(2
6
32
– 1)t
SCLK
Unit
ns
ns
ns
ns
ns
ns