ADSP-21369BSWZ-1A Analog Devices Inc, ADSP-21369BSWZ-1A Datasheet - Page 13
![IC DSP 32BIT 266MHZ 208-LQFP](/photos/6/71/67136/sw-208_sml.jpg)
ADSP-21369BSWZ-1A
Manufacturer Part Number
ADSP-21369BSWZ-1A
Description
IC DSP 32BIT 266MHZ 208-LQFP
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheet
1.ADSP-21369KBPZ-2A.pdf
(60 pages)
Specifications of ADSP-21369BSWZ-1A
Package / Case
208-LQFP
Interface
DAI, DPI
Operating Temperature
-40°C ~ 85°C
Clock Rate
266MHz
Non-volatile Memory
ROM (768 kB)
On-chip Ram
256kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Mounting Type
Surface Mount
Svhc
No SVHC (18-Jun-2010)
Base Number
21369
Core Frequency Typ
266MHz
Dsp Type
Floating Point
Mmac
800
No. Of Pins
208
Interface Type
SPI, UART
Rohs Compliant
Yes
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21369BSWZ-1A
Manufacturer:
Analog Devices Inc
Quantity:
10 000
PIN FUNCTION DESCRIPTIONS
The following symbols appear in the Type column of
A = asynchronous, G = ground, I = input, O = output,
O/T = output three-state, P = power supply, S = synchronous,
(A/D) = active drive, (O/D) = open-drain, (pd) = pull-down
resistor, (pu) = pull-up resistor.
Table 8. Pin Descriptions
Name
ADDR
DATA
ACK
MS
RD
WR
FLAG[0]/IRQ0
FLAG[1]/IRQ1
FLAG[2]/IRQ2/
MS
FLAG[3]/
TMREXP/MS
0–1
2
31–0
23–0
3
Type
O/T (pu)
I/O (pu)
I (pu)
O/T (pu)
O/T (pu)
O/T (pu)
I/O
I/O
I/O with pro-
grammable pu
(for MS mode)
I/O with pro-
grammable pu
(for MS mode)
1
1
1
1
1
1
State During/
After Reset
(ID = 00x)
Pulled high/
driven low
Pulled high/
pulled high
Pulled high/
driven high
Pulled high/
driven high
Pulled high/
driven high
FLAG[0] INPUT
FLAG[1] INPUT
FLAG[2] INPUT
FLAG[3] INPUT
Rev. E | Page 13 of 60 | July 2009
Table
Description
External Address. The processors output addresses for external memory and peripher-
als on these pins.
External Data. Data pins can be multiplexed to support external memory interface data
(I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins are in EMIF mode
and FLAG(0-3) pins are in FLAGS mode (default). When configured using the
IDP_PDAP_CTL register, IDP Channel 0 scans the external port data pins for parallel input
data.
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an
external memory access. ACK is used by I/O devices, memory controllers, or other periph-
erals to hold off completion of an external memory access.
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-
sponding banks of external memory. The MS
that change at the same time as the other address lines. When no external memory access
is occurring, the MS
memory access instruction is executed, whether or not the condition is true.
The MS
reference for more information.
External Port Read Enable. RD is asserted whenever the processors read a word from
external memory.
External Port Write Enable. WR is asserted when the processors write a word to external
memory.
FLAG0/Interrupt Request 0.
FLAG1/Interrupt Request 1.
FLAG2/Interrupt Request 2/Memory Select 2.
FLAG3/Timer Expired/Memory Select 3.
8:
1
pin can be used in EPORT/FLASH boot mode. See the processor hardware
ADSP-21367/ADSP-21368/ADSP-21369
The ADSP-21367/ADSP-21368/ADSP-21369 SHARC proces-
sors use extensive pin multiplexing to achieve a lower pin count.
For complete information on the multiplexing scheme, see the
ADSP-21368 SHARC Processor Hardware Reference, “System
Design” chapter.
3-0
lines are inactive; they are active, however, when a conditional
3-0
lines are decoded memory address lines