ADSP-21369BSWZ-1A Analog Devices Inc, ADSP-21369BSWZ-1A Datasheet - Page 38
![IC DSP 32BIT 266MHZ 208-LQFP](/photos/6/71/67136/sw-208_sml.jpg)
ADSP-21369BSWZ-1A
Manufacturer Part Number
ADSP-21369BSWZ-1A
Description
IC DSP 32BIT 266MHZ 208-LQFP
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheet
1.ADSP-21369KBPZ-2A.pdf
(60 pages)
Specifications of ADSP-21369BSWZ-1A
Package / Case
208-LQFP
Interface
DAI, DPI
Operating Temperature
-40°C ~ 85°C
Clock Rate
266MHz
Non-volatile Memory
ROM (768 kB)
On-chip Ram
256kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Mounting Type
Surface Mount
Svhc
No SVHC (18-Jun-2010)
Base Number
21369
Core Frequency Typ
266MHz
Dsp Type
Floating Point
Mmac
800
No. Of Pins
208
Interface Type
SPI, UART
Rohs Compliant
Yes
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21369BSWZ-1A
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21367/ADSP-21368/ADSP-21369
Input Data Port
The timing requirements for the IDP are given in
signals SCLK, frame sync (FS), and SDATA are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 32. IDP
1
Parameter
Timing Requirements
t
t
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Clock Width
Clock Period
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SDATA)
(SCLK)
(FS)
Table
Rev. E | Page 38 of 60 | July 2009
Figure 25. IDP Master Timing
t
IPDCLKW
32. IDP
t
SISFS
SAMPLE EDGE
t
SISD
t
t
SIHFS
SIHD
t
IPDCLK
Min
4
2.5
2.5
2.5
(t
t
PCLK
PCLK
× 4
× 4) ÷ 2 – 1
Max
Unit
ns
ns
ns
ns
ns
ns