ADSP-2189MKSTZ-300 Analog Devices Inc, ADSP-2189MKSTZ-300 Datasheet - Page 20
![IC DSP CONTROLLER 16BIT 100-LQFP](/photos/6/59/65915/st-100_sml.jpg)
ADSP-2189MKSTZ-300
Manufacturer Part Number
ADSP-2189MKSTZ-300
Description
IC DSP CONTROLLER 16BIT 100-LQFP
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet
1.ADSP-2189MBSTZ-266.pdf
(32 pages)
Specifications of ADSP-2189MKSTZ-300
Interface
Host Interface, Serial Port
Clock Rate
75MHz
Non-volatile Memory
External
On-chip Ram
192kB
Voltage - I/o
3.30V
Voltage - Core
2.50V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
No. Of Bits
16
Frequency
77MHz
Supply Voltage
3.3V
Embedded Interface Type
Host Port, Serial
No. Of Mips
75
Supply Voltage Range
2.37V To 3.6V
Operating Temperature Range
0°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADSP-2189MKSTZ300
ADSP-2189MKSTZ300
ADSP-2189MKSTZ300
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-2189MKSTZ-300
Manufacturer:
SMD
Quantity:
272
Company:
Part Number:
ADSP-2189MKSTZ-300
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-2189MKSTZ-300
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADSP-2189M
Parameter
Interrupts and Flags
Timing Requirements:
t
t
Switching Characteristics:
t
t
NOTES
1
2
3
4
5
IFS
IFH
FOH
FOD
If IRQx and FI inputs meet t
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further
information on interrupt servicing.)
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
Flag Outputs = PFx, FL0, FL1, FL2, Flag_out4.
IFS
and t
IRQx, FI, or PFx Setup before CLKOUT Low
IRQx, FI, or PFx Hold after CLKOUT High
Flag Output Hold after CLKOUT Low
Flag Output Delay from CLKOUT Low
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
OUTPUTS
CLKOUT
FLAG
IRQx
PFx
FI
Figure 23. Interrupts and Flags
t
FOH
t
FOD
–20–
5
5
t
1, 2, 3, 4
IFH
1, 2, 3, 4
t
IFS
Min
0.25t
0.25t
0.5t
CK
CK
CK
– 5
+ 10
Max
0.5t
CK
+ 4
REV. A
Unit
ns
ns
ns
ns