DSPB56721AG Freescale Semiconductor, DSPB56721AG Datasheet

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... Included among the new modules are an Asynchronous Sample Rate Converter (ASRC), Inter-Core Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: DSP56720EC DSP56720/DSP56721 DSP56720 144-Pin LQFP 20 mm × ...

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... Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DSP56720/DSP56721 Multi-Core Audio Processors, Rev Programming the SHI I C Serial Clock . . . . . . 26 Enhanced Serial Audio Interface (ESAI) Timing 27 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32 JTAG Timing Watchdog Timer Timing . . . . . . . . . . . . . . . . . . 35 Host Data Interface (HDI24) Timing . . . . . . . . . 35 S/PDIF Timing . . . . . . . . . . . . . . . . . . . . . . . . . 42 EMC Timing (DSP56720 Only Freescale Semiconductor ...

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... Core-0 On-Chip Memory PCU / AGU DMA OnCE / ALU MODA0, MODB0, MODC0, MODD0 ™ Symphony Freescale Semiconductor EXTAL/XTAL CGM ASRC Arbiter 9 Arbiter 8 Shared Bus 0 Shared Bus 1 Arbiters 0–7 Shared Memory 8 Kbytes Blocks 0–7 (64 Kbytes total) 2 JTAGs JTAG Figure 1. DSP56720 Block Diagram EXTAL/XTAL ...

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... Section 1.1, “Pinout for DSP56720 144-Pin Plastic LQFP Table 1. Pin Assignments by Package Package 144-pin plastic LQFP Figure 3 on page 5 80-pin plastic LQFP Figure 4 on page 6 144-pin plastic LQFP Figure 5 on page 7 DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Package.” See Freescale Semiconductor ...

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... IO_VDD 29 IO_GND 30 PLLP1_GND 31 PLLP1_VDD 32 PLLD1_GND 33 PLLD1_VDD 34 PLLA1_GND 35 PLLA1_VDD 36 Figure 3. DSP56720 144-Pin Package Pinout ™ Symphony Freescale Semiconductor DSP56720 144-Pin DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 108 IO_GND 107 IO_VDD 106 WDT 105 PINIT/NMI 104 TDO 103 TDI 102 TCK 101 TMS 100 ...

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... SCKT_3 15 GND 16 GND 17 GND 18 GND 19 GND 20 ™ Symphony 6 DSP56721 80-Pin Figure 4. DSP56721 80-Pin Package DSP56720/DSP56721 Multi-Core Audio Processors, Rev WDT 59 PINIT/NMI 58 TDO 57 TDI 56 TCK 55 TMS 54 CORE_GND 53 CORE_VDD 52 SDO4/SDI1 51 SDO5/SDI0 50 IO_GND 49 IO_VDD 48 EXTAL 47 XTAL 46 PLLP_GND 45 PLLD_GND 44 PLLD_VDD 43 PLLA_GND 42 PLLA_VDD 41 PLLP_VDD Freescale Semiconductor ...

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... Figure 5. DSP56721 144-Pin Package Pinout 1.4 Pin Multiplexing Many pins are multiplexed. For more about pin multiplexing, refer to the Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors Reference Manual (DSP56720RM). ™ Symphony Freescale Semiconductor DSP56721 144-Pin DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 108 IO_GND 107 ...

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... Symphony 8 CAUTION NOTE Table 2. Maximum Ratings Symbol V CORE_VDD, V PLLD_VDD V PLLP_VDD, V IO_VDD PLLA_VDD and GND I I lsync_out I lclk I ale I JTAG T J DSP56720/DSP56721 Multi-Core Audio Processors, Rev The suggested Value Unit –0 1.26 V –0 4 GND –0 ° –40 to +100 C Freescale Semiconductor ...

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... I/O INT 780 mA. See Table 4 for more information. To find T at 100° C using the worst-case conditions and a four-layer board ™ Symphony Freescale Semiconductor Table 2. Maximum Ratings (Continued) Symbol T STG — — Table 3. Thermal Characteristics Board Type 1,2 Single layer board (1s) ...

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... V must be power up before the analog 3.3 V power. Similarly, for power down the digital (IO) 3.3 V must be power down after the analog power 3.3 V. This requirement is for avoiding possible leakage. Core_VDD Figure 8. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD ™ Symphony 10 IO_VDD Core_VDD must be < DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 External Schottky Diode 1.0 V Freescale Semiconductor ...

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... F1=low frequency (any specified operating frequency lower than F2) F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application. ™ Symphony Freescale Semiconductor × × ...

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... DD V 3.14 3.3 3.46 DDIO V –0.3 — 0 — — ± — 18 — –10 — 10 TSI V 2.4 — — — — 0 142 157 PD I — 224 445 CCI I — 121 353 CCW I — 90 327 CCS Freescale Semiconductor Unit μA pF μ kΩ kΩ ...

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... External Clock Operation The DSP56720/DSP56721 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see the example in ™ Symphony Freescale Semiconductor and V reference levels set at 0.4 V and 2.4 V, respectively Table 5 ...

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... Figure 9. Using the On-Chip Oscillator ETH ETL ETC + Figure 10. External Clock Timing Table 6. Clock Operation Symbol Eth Etl Etc Tc DSP56720/DSP56721 Multi-Core Audio Processors, Rev Midpoint Min Max 16.67 100 2.5 inf 16.67 100 2.5 inf 5 inf 33.3 500 5.00 inf 5.00 5120 Freescale Semiconductor Units ...

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... Interrupt Requests Rate • ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1 • DMA • IRQ, NMI (edge trigger) • IRQ (level trigger) ™ Symphony Freescale Semiconductor 3 DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Expression Min Max — — × — ...

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... RESET All Pins ™ Symphony Reset Value Figure 11. Reset Timing Diagram DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Expression Min Max 6 × T — 30 × T — 35 × T — 10 × T — 15 valid, and the EXTAL input is active and Freescale Semiconductor Unit ...

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... Figure 12. External Fast Interrupt Timing Diagram Figure 13 shows the negative edge-triggered external interrupt timing diagram. IRQA, IRQB, IRQC, IRQD, NMI, NMI_1 IRQA, IRQB, IRQC, IRQD, NMI, NMI_1 Figure 13. External Interrupt Timing Diagram (Negative Edge-Triggered) ™ Symphony Freescale Semiconductor DSP56720/DSP56721 Multi-Core Audio Processors, Rev ...

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... SPICC 0.5 × 29.5 — SPICC 0.5 × 91.5 — SPICC 0.5 × 186.5 — SPICC 2.0 × 19.6 29.6 — C 2.0 × 19.6 29.6 — C 2.0 × 86.6 96.6 — C 2.0 × 186.6 196.6 — C Freescale Semiconductor Unit ...

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... Data input valid to SCK edge (data input set-up time) 30 SCK last sampling edge to data input not valid 31 SS assertion to data out active 32 SS deassertion to data high impedance ™ Symphony Freescale Semiconductor Mode Filter Mode Master Bypassed Very Narrow Narrow Wide Slave Bypassed Very Narrow ...

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... T + 130 150.0 — C 3.0 × 45.0 — C 2.0 × T 10.0 — C 0.5 × 3.0 × 49.5 — SPICC 3.0 × 49.5 — SPICC 0.5 × 3.0 × 111.5 — SPICC 0.5 × 3.0 × 206.5 — SPICC Freescale Semiconductor Unit ...

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... All times assume internal clock frequency of 200 MHz. 5. SHI_1 specs match those of SHI. SS (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) 29 MISO (Input) MOSI (Output) 40 HREQ (Input) Figure 15. SPI Master Timing Diagram (CPHA = 0) ™ Symphony Freescale Semiconductor Mode Filter Mode Master — Master — Master — pF ...

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... SS (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) MISO (Input) MOSI (Output) 40 HREQ (Input) Figure 16. SPI Master Timing Diagram (CPHA = 1) ™ Symphony MSB Valid 33 MSB DSP56720/DSP56721 Multi-Core Audio Processors, Rev LSB Valid 34 LSB Freescale Semiconductor ...

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... SS (Input) SCK (CPOL = 0) (Input) SCK (CPOL = 1) (Input) 31 MISO (Output) 29 MOSI (Input) HREQ (Output) Figure 17. SPI Slave Timing Diagram (CPHA = 0) ™ Symphony Freescale Semiconductor MSB 30 MSB Valid 36 DSP56720/DSP56721 Multi-Core Audio Processors, Rev LSB 29 30 LSB Valid 38 23 ...

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... DSP56720/DSP56721 Multi-Core Audio Processors, Rev LSB 29 30 LSB Valid 37 36 Fast-Mode Max Min Max 0 — — — 50 100 — 100 100 — 400 — 2.5 — — 1.3 — — 0.6 — — 0.6 — Freescale Semiconductor Unit kHz μs μs μs μs ...

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... Wide filters enabled 59 Last SCL edge to HREQ output not 2 deasserted • Filters bypassed • Very Narrow filters enabled • Narrow filters enabled • Wide filters enabled ™ Symphony Freescale Semiconductor 2 C Protocol Timing Parameters (Continued) 2 Standard I C Standard Symbol/ Expression Min T 4 ...

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... SCL Serial Clock Cycle (TSCL) generated as master) R ™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Standard Fast-Mode Max Min Max — 927 — — 917 — — 877 — — 827 — — 0.0 — Freescale Semiconductor Unit Eqn. 4 Eqn. 5 Eqn SCL Eqn. 7 ...

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... SCKR rising edge to FSR out (bl) high 66 SCKR rising edge to FSR out (bl) low 67 SCKR rising edge to FSR out (wr) high 68 SCKR rising edge to FSR out (wr) low 69 SCKR rising edge to FSR out (wl) high 70 SCKR rising edge to FSR out (wl) low ™ Symphony Freescale Semiconductor MSB Figure 19. I ...

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... Freescale Semiconductor Unit ...

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... Periodically sampled and not 100% tested. 8. ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI. ™ Symphony Freescale Semiconductor Symbol Expression — — ...

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... Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. Figure 20. ESAI Transmitter Timing Diagram ™ Symphony First Bit DSP56720/DSP56721 Multi-Core Audio Processors, Rev Last Bit 88 91 See Note Freescale Semiconductor ...

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... SCKR (Input/Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In Flags In HCKT SCKT (Output) ™ Symphony Freescale Semiconductor First Bit Figure 21. ESAI Receiver Timing Diagram 95 96 Figure 22. ESAI HCKT Timing Diagram DSP56720/DSP56721 Multi-Core Audio Processors, Rev Last Bit ...

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... Figure 25 Table 12. GPIO Timing Parameters 1 Characteristics DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Unit Min Max + 2.0 12.0 — 2.0 12.0 — shows the timing diagram. Expression Min Max — — 7 — — 7 — 2 — — 0 — 2 × — Freescale Semiconductor Unit ...

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... TCK rise and fall times 112 Boundary scan input data setup time 113 Boundary scan input data hold time 114 TCK low to output data valid 115 TCK low to output high impedance ™ Symphony Freescale Semiconductor 1 Characteristics = –40°C to 100° 102 103 Valid 104 106 Figure 25 ...

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... Output Data Valid 115 114 Output Data Valid Figure 27. Debugger Port Timing Diagram DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 All Frequencies Min Max 5.0 — 25.0 — — 44.0 — 44.0 110 V M 111 VIH 112 113 Input Data Valid Freescale Semiconductor Unit ...

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... Read data strobe deassertion width 3 after “Last Data Register” reads 4,5 , 319 or between two consecutive CVR, ICR, or ISR reads 6 HACK deassertion width after “Last Data Register” reads ™ Symphony Freescale Semiconductor 116 Input Data Valid 118 Output Data Valid 119 ...

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... T + 9.9 14.9 — — 9.9 — ns — — 19.1 ns — 0.0 — ns — 4.7 — ns — 3.3 — ns — 0 — ns — 4.7 — — 3.3 — 5.0 — Freescale Semiconductor ...

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... The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode. 10. In this calculation, the host request signal is pulled 4.7 kW resistor in the open-drain mode. 11. HDI24_1 specs match those of HDI24. ™ Symphony Freescale Semiconductor = 50 pF. L DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 200 MHz ...

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... HD23 HOREQ, HRRQ, HTRQ Figure 30. HDI24 Read Timing Diagram, Non-Multiplexed Bus ™ Symphony 38 317 327 326 336 337 330 317 328 332 327 326 340 341 DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 318 328 329 333 318 319 329 338 Freescale Semiconductor ...

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... HA0 HWR, HDS HD0 Figure 31. HDI24 Write Timing Diagram, Non-Multiplexed Bus ™ Symphony Freescale Semiconductor – HA2 336 331 HCS 320 324 – HD23 340 341 HOREQ, HRRQ, HTRQ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 337 333 321 325 339 39 ...

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... HAD23 HOREQ, HRRQ, HTRQ Figure 32. HDI24 Read Timing Diagram, Multiplexed Bus ™ Symphony 40 HA10 336 322 HAS 323 317 334 335 327 Address 326 340 341 DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 337 318 319 328 329 Data 338 Freescale Semiconductor ...

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... HWR, HDS HAD0 –HAD23 HOREQ, HRRQ, HTRQ Figure 33. HDI24 Write Timing Diagram, Multiplexed Bus HOREQ (Output) H0–H23 Figure 34. HDI24 Host DMA Write Timing Diagram ™ Symphony Freescale Semiconductor 336 323 320 334 324 335 Address 340 341 342 343 344 320 ...

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... Figure 36 and Figure 37 All Frequency Min Max — 0.7 — 1.5 — 24.2 — 31.3 — 1.5 — 13.6 — 18.0 40.0 — 16.0 — 16.0 — 40.0 — 16.0 — 16.0 — Freescale Semiconductor show the Unit ...

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... Reference Manual explains in detail the interfacing and features of EMC. The applicable sections are as follows: • Section 22.4.4.3, “UPM Signal Timing” • Section 22.4.4.7, “Memory System Interface Example Using UPM” ™ Symphony Freescale Semiconductor srckp srckpl V M Figure 36. S/PDIF SRCK Timing Diagram stclkp ...

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... LGPL[5:0] LAD[23:0] LALE Figure 38. EMC Signals (EMC PLL Enabled; LCRR[CLKDIV ™ Symphony 44 T clk T clk_skew T sync_in_skew T in_s asynchronous input T gta T asynchronous input upwait T T out_s out_h T ad_z T T ad_s ad_h T T ale_h ale DSP56720/DSP56721 Multi-Core Audio Processors, Rev in_h Freescale Semiconductor ...

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... Output hold from LCLK (except LAD[23:0] and LALE) LAD[23:0] output setup from LCLK LAD[23:0] output hold from LCLK LCLK to output high impedance for LAD[23:0] Notes negative hold time means that the signal could be invalid before the LCLK rising edge. ™ Symphony Freescale Semiconductor Symbol ...

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... DSP56720/DSP56721 Multi-Core Audio Processors, Rev clk T in_h Symbol Min Max T 40 — clk T 8 — in_s T –1 — in_h T 42 — gta T 42 — upwait T 5 — ale_h T 34 — ale T 19 — out_s T 18 — out_h Freescale Semiconductor Unit ...

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... LALE Figure 40. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV Functional Description and Application Information See the Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors Reference Manual (DSP56720RM) for detailed functional and applications information. ™ Symphony Freescale Semiconductor T in_s asynchronous input T gta T asynchronous input upwait ...

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... DSPA56720CAG –40°C–85°C DSPB56720CAG –40°C–85°C DSPC56720CAG –40°C–85°C DSPA56721AG 0°C–70°C DSPB56721AG 0°C–70°C DSPC56721AG 0°C–70°C DSPA56721AF 0°C–70°C DSPB56721AF 0°C–70°C DSPC56721AF 0°C–70°C DSPA56721CAG – ...

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... Package Outline Drawing Figure 41 and Figure 42 show the 80-pin package outline drawings. Figure 41. 80-Pin Package Outline Drawing ( ™ Symphony Freescale Semiconductor DSP56720/DSP56721 Multi-Core Audio Processors, Rev ...

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... Dimensions do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions include mold mismatch and are determined at datum plane H. 7 Dimension does not include dambar protrusion. Dambar protrusion shall not cause the lead width to exceed 0.46 mm. Minimnum space between protrusion and adjacent lead or protrusion 0.07 mm. ™ Symphony 50 DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor ...

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... Package Outline Drawing Figure 43 and Figure 44 show the 144-pin package drawings. Figure 43. 144-Pin Package Outline Drawing ( ™ Symphony Freescale Semiconductor DSP56720/DSP56721 Multi-Core Audio Processors, Rev ...

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... This dimension does not include dambar protrusion. Protrusions shall not cause the lead width to exceed 0.35 mm minimum space between protrusion and an adjacent lead shall be 0.07 mm. ™ Symphony 52 DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor ...

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... This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. Documentation is available from a local Freescale Semiconductor, Inc. distributor, semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information) ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...