DSPB56721AG Freescale Semiconductor, DSPB56721AG Datasheet - Page 26

• Manufacturer Part Number: DSPB56721AG
• Description: AUDIO PROCESSOR SYMPH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56721AG

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: External
• On-chip Ram: 744kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes:
1. V
2. Pull-up resistor: R
3. Capacitive load: C
4. All times assume noise free inputs.
5. All times assume internal clock frequency of 200 MHz.
6. SHI_1 specs match those of SHI.
7. Master Mode
2.12
The programmed serial clock cycle, T
control register).
The expression for T
where
In I
to
The programmed serial clock cycle (T
shown in Equation 4.
26
No.
60
61
2
CORE_VDD
C mode, the user may select a value for the programmed serial clock cycle from
HREQ in assertion to first SCL edge
First SCL edge to HREQ is not asserted
(HREQ in hold time.)
• Filters bypassed
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
— HRS is the pre scaler rate select bit. When HRS is cleared, the fixed
— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be
T
I
Programming the SHI I
2
CCP
divide-by-eight pre scaler is operational. When HRS is set, the pre scaler is bypassed.
selected.
= 1.00± 0.10 V; T
Characteristics
+ 3 × T
P
b
I
(min) = 1.5kΩ.
2
(max) = 50 pF.
CCP
Symphony
C
is
+ 45ns + T
T
Table 9. SHI I
I
2
CCP
J
= –40°C to 100°C; C
1,2,3,4,5
4096 × T
= [T
6 × T
™
I
I
2
2
CCP
DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5
CCP
R
C
× 2 × (HDM[7:0] + 1) × (7 × (1 — HRS) + 1)]
C
, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock
) should be chosen in order to achieve the desired SCL serial clock cycle (T
C
2
(Nominal, SCL Serial Clock Cycle (TSCL) generated as master)
C Protocol Timing Parameters (Continued)
(if HDM[7:0] = $02 and HRS = 1)
(if HDM[7:0] = $FF and HRS = 0)
2
Expression
L
C Serial Clock
Symbol/
T
t
= 50 pF.
HO;RQI
AS;RQI
Standard I
2
C
4327
4317
4282
4227
Min
0.0
Standard
Max
—
—
—
—
—
Min
927
917
877
827
0.0
Fast-Mode
Freescale Semiconductor
Max
—
—
—
—
—
SCL
Eqn. 4
Eqn. 5
Eqn. 6
Eqn. 7
Unit
ns
ns
ns
ns
ns
), as