ADSP-21061LKS-160 Analog Devices Inc, ADSP-21061LKS-160 Datasheet - Page 22
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ADSP-21061LKS-160
Manufacturer Part Number
ADSP-21061LKS-160
Description
IC DSP CONTROLLER 1MBIT 240MQFP
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheet
1.ADSP-21061LKSZ-160.pdf
(56 pages)
Specifications of ADSP-21061LKS-160
Rohs Status
RoHS non-compliant
Interface
Synchronous Serial Port (SSP)
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
128kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
240-MQFP, 240-PQFP
Device Core Size
32b
Architecture
Super Harvard
Format
Floating Point
Clock Freq (max)
40MHz
Mips
40
Device Input Clock Speed
40MHz
Ram Size
128KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
MQFP
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21061LKS-160
Manufacturer:
AD
Quantity:
5 510
Company:
Part Number:
ADSP-21061LKS-160
Manufacturer:
3COM
Quantity:
5 510
Part Number:
ADSP-21061LKS-160
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADSP-21061/ADSP-21061L
Clock Input
Table 7. Clock Input
Reset
Table 8. Reset
1
2
Parameter
Timing Requirements
t
t
t
t
Parameter
Timing Requirements
t
t
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
Only required if multiple ADSP-21061s must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21061s commu-
CK
CKL
CKH
CKRF
WRST
SRST
V
nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
DD
and CLKIN (not including startup time of external clock oscillator).
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
RESET Pulse Width Low
RESET Setup Before CLKIN High
RESET
CLKIN
CLKIN
1
2
Min
20
7
5
ADSP-21061
50 MHz, 5 V
Rev. C | Page 22 of 56 | July 2007
Figure 9. Clock Input
t
Max
100
3
Figure 10. Reset
CKH
Min
22.5
7
5
t
WRST
ADSP-21061L
44 MHz, 3.3 V
t
t
CK
CKL
Min
4t
14 + DT/2
CK
Max
100
3
Min
25
7
5
ADSP-21061L
ADSP-21061/
5 V and 3.3 V
t
SRST
5 V and 3.3 V
40 MHz,
Max
100
3
Max
t
CK
Min
30
7
5
ADSP-21061
33 MHz, 5 V
Max
100
3
Unit
ns
ns
Unit
ns
ns
ns
ns