ADSP-21061LKS-160 Analog Devices Inc, ADSP-21061LKS-160 Datasheet - Page 26
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ADSP-21061LKS-160
Manufacturer Part Number
ADSP-21061LKS-160
Description
IC DSP CONTROLLER 1MBIT 240MQFP
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheet
1.ADSP-21061LKSZ-160.pdf
(56 pages)
Specifications of ADSP-21061LKS-160
Rohs Status
RoHS non-compliant
Interface
Synchronous Serial Port (SSP)
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
128kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
240-MQFP, 240-PQFP
Device Core Size
32b
Architecture
Super Harvard
Format
Floating Point
Clock Freq (max)
40MHz
Mips
40
Device Input Clock Speed
40MHz
Ram Size
128KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
MQFP
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21061LKS-160
Manufacturer:
AD
Quantity:
5 510
Company:
Part Number:
ADSP-21061LKS-160
Manufacturer:
3COM
Quantity:
5 510
Part Number:
ADSP-21061LKS-160
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADSP-21061/ADSP-21061L
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is the
Table 13. Memory Write—Bus Master
1
2
3
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register) × t
H = t
I = t
ACK delay/setup: User must meet t
The falling edge of MSx, SW, BMS is referenced.
For more information, see
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DATRWH
WWR
DDWR
WDE
SADADC
(high).
CK
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
ACK Delay from Address, Selects
ACK Delay from WR Low
Address, Selects to WR Deasserted
Address, Selects to WR Low
WR Pulse Width
Data Setup Before WR High
Address Hold After WR Deasserted
Data Disable After WR Deasserted
WR High to WR, RD, DMAGx Low
Data Disable Before WR or RD Low
WR Low to Data Enabled
Address, Selects to ADRCLK High
ADDRESS
RD, DMAG
MSX, SW
ADRCLK
BMS
(OUT)
DATA
ACK
WR
Example System Hold Time Calculation on Page 44
DAAK
or t
1
t
SADADC
DSAK
t
DAWL
2
or synchronous specification t
t
DAAK
1, 2
2
3
2
t
Figure 15. Memory Write—Bus Master
DSAK
Rev. C | Page 26 of 56 | July 2007
t
WDE
CK
.
t
DAWH
for calculation of hold times given capacitive and dc loads.
SAKC
for deassertion of ACK (low), all three specifications must be met for assertion of ACK
t
WW
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
DMAGx strobe timing parameters only applies to asynchronous
access mode.
Min
17 + 15DT/16 + W
3 + 3DT/8
13 + 9DT/16 + W
7 + DT/2 + W
1 + DT/16 + H
1 + DT/16 +H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
0 + DT/4
t
DDWH
5 V and 3.3 V
t
DATRWH
t
DWHA
Max
15 + 7DT/8 + W
8 + DT/2 + W
6 + DT/16+H
t
WWR
t
DDWR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns