ADSP-2185KST-133 Analog Devices Inc, ADSP-2185KST-133 Datasheet

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... DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory. The ADSP-2185 integrates 80K bytes of on-chip memory con- figured as 16K words (24-bit) of program RAM and 16K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equip- ment ...

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... ADSP-218x based evaluation board with PC monitor software plus Assembler, Linker, Simulator and PROM Splitter software. The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hard- ware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: • ...

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... The ADSP-2185 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2185 SPORTs. For additional information on Serial Ports, refer to the ADSP- 2100 Family User’s Manual. • SPORTs are bidirectional and have a separate, double-buff- ered transmit and receive section. • ...

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... SPORT configuration determined by the DSP System Control Register. Soft- ware configurable. Memory Interface Pins The ADSP-2185 processor can be used in one of two modes, Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities ...

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... The CLKOUT pin may also be disabled to reduce external power dissipation. Power-Down The ADSP-2185 processor has a low power feature that lets the processor enter a very low power dormant state through hard- ware or software control. Here is a brief list of power-down features. Refer to the ADSP-2100 Family User’s Manual, “System Interface” ...

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... IAD15-0 Figure 2. Basic System Configuration Clock Signals The ADSP-2185 can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal opera- tion. The only exception is while the processor is in the power- down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’ ...

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... The ADSP-2185 contains a 16K 24 on-chip program RAM. The on-chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle. In addition, the ADSP-2185 allows the use of 8K external memory overlays. The program memory space organization is controlled by the is Mode B pin and the PMOVLAY register ...

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... EXTERNAL 0x0000 Figure 5. Program Memory (Mode Data Memory The ADSP-2185 has 16,352 16-bit words of internal data memory. In addition, the ADSP-2185 allows the use of 8K external memory overlays. Figure 6 shows the organization of the data memory. DATA MEMORY ADDRESS 32 MEMORY– MAPPED REGISTERS ...

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... Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and the ADSP-2185. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’ ...

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... Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, • Asserting the bus grant (BG) signal and • Halting program execution Mode is enabled, the ADSP-2185 will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2185 is performing an external memory access ...

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... The EZ-ICE * uses the EE (emulator enable) signal to take control of the ADSP-2185 in the target system. This causes the processor to use its ERESET, EBR and EBG pins instead of the RESET, BR and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. ...

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... DSP components statisti- * probe onto the cally vary in switching characteristic and timing requirements within published limits. Restriction: All memory strobe signals on the ADSP-2185 (RD WR, PMS, DMS, BMS, CMS and IOMS) used in your target system must have 10 k pull-up resistors connected when the BR ® ...

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... V on BR, CLKIN Inactive. 9 Idle refers to ADSP-2185 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V 10 IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. ...

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... Permanent damage may occur to devices subjected to high energy electrostatic discharges. The ADSP-2185 features proprietary ESD protection circuitry to dissipate high energy discharges (Human Body Model) per method 3015 of MIL-STD-883. Proper ESD precautions are recom- mended to avoid performance degradation or loss of functionality ...

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... DD f 33.3 MHz = 66.6 mW VALID FOR ALL TEMPERATURE GRADES. 16.67 MHz = 37 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 16.67 MHz = 4 IDLE REFERS TO ADSP-2185 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V 33.3 MHz = 8 TYPICAL POWER DISSIPATION AT 5.0V V 116 ...

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... ADSP-2185 CAPACITIVE LOADING Figures 9 and 10 show the capacitive loading characteristics of the ADSP-2185 + 4. 100 150 50 C – Figure 9. Typical Output Rise Time vs. Load Capacitance, C (at Maximum Ambient Operating Temperature NOMINAL –2 –4 –6 0 100 50 C – Figure 10. Typical Output Valid Delay or Hold vs. Load ...

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... Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). CLKIN CLKOUT * PF(2:0) RESET REV. 0 Min 0.5 t – 0.5 t – CKI t CKIH t CKIL t CKCH t CKH t CKL PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A Figure 14. Clock Signals –17– ADSP-2185 Max Unit 150 ...

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... IFS IFH the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced. ...

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... asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue. ...

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... ADSP-2185 Parameter Memory Read Timing Requirements Low to Data Valid RDD t A0-A13, xMS to Data Valid AA t Data Hold from RD High RDH Switching Characteristics Pulse Width RP t CLKOUT High to RD Low CRD t A0–A13, xMS Setup before RD Low ASR t A0–A13, xMS Hold after RD Deasserted ...

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... CLKOUT A0–A13 DMS, PMS, BMS, CMS, IOMS REV. 0 Min 0.5 t – 0.25 t – 0.5 t – 0.25 t – 0.25 t – 0.25 t – 0.75 t – 0.25 t – 0.5 t – WRA ASW WWR CWR WDE Figure 18. Memory Write –21– ADSP-2185 Max Unit 0. DDR ...

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... ADSP-2185 Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid SCDV t TFS/RFS ...

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... Start of Address Latch = IS Low and IAL High. 2 Start of Write or Read = IS Low and IWR Low or IRD Low. 3 End of Address Latch = IS High or IAL Low. IACK IAL IS IAD 15–0 IRD OR IWR REV. 0 Min IKA t IALP t t IASU IAH t IALS Figure 20. IDMA Address Latch –23– ADSP-2185 Max Unit ...

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... ADSP-2185 Parameter IDMA Write, Short Write Cycle Timing Requirements: t IACK Low before Start of Write IKW Duration of Write IWP t IAD15–0 Data Setup before End of Write IDSU t IAD15–0 Data Hold after End of Write IDH Switching Characteristics: t Start of Write to IACK High IKHW ...

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... If Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual. IACK IS IWR IAD 15– ...

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... ADSP-2185 Parameter IDMA Read, Long Read Cycle Timing Requirements: t IACK Low before Start of Read IKR 1 t Duration of Read IRP Switching Characteristics: t IACK High after Start of Read IKHR t IAD15–0 Data Setup before IACK Low IKDS t IAD15–0 Data Hold after End of Read ...

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... IAD15–0 Previous Data Valid after Start of Read IRDV NOTES 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High. REV. 0 Min IACK t IKR t IKHR IS t IRP IRD t IRDE PREVIOUS IAD 15–0 DATA t IRDV Figure 24. IDMA Read, Short Read Cycle –27– ADSP-2185 Max Unit IKDH t IKDD ...

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... A12/IAD11 A13/IAD12 11 12 GND CLKIN 13 14 XTAL 15 VDD 16 CLKOUT 17 GND 18 VDD BMS 21 DMS 22 PMS 23 IOMS 24 CMS 25 100-Lead TQFP Package Pinout ADSP-2185 TOP VIEW (Not to Scale) –28– 75 D15 74 D14 73 D13 72 D12 71 GND 70 D11 69 D10 VDD 66 GND D7/IWR 63 D6/IRD 62 D5/IAL 61 D4/IS ...

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... The ADSP-2185 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. ...

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... ADSP-2185 Ambient Temperature Part Number Range ADSP-2185KST-115 +70 C ADSP-2185BST-115 – +85 C ADSP-2185KST-133 +70 C ADSP-2185BST-133 – +85 C *ST = Plastic Thin Quad Flatpack (TQFP). 100-Lead Metric Thin Plastic Quad Flatpack (TQFP) 0.024 (0.75) 0.022 (0.60) TYP 0.020 (0.50) ORDERING GUIDE Instruction Rate (MHz) 28.8 28 ...

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