ADSP-21992BST Analog Devices Inc, ADSP-21992BST Datasheet - Page 9

• Manufacturer Part Number: ADSP-21992BST
• Description: IC DSP CONTROLLER 16BIT 176LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-21992BST

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP
• Clock Rate: 160MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP

CONTROLLER AREA NETWORK (CAN) MODULE
The ADSP-21992 contains a controller area network (CAN)
module. Key features of the CAN module are:
The CAN module is a low baud rate serial interface intended for
use in applications where baud rates are typically under 1 Mbps.
The CAN protocol incorporates a data CRC check, message
error tracking and fault node confinement as means to improve
network reliability to the level required for control applications.
The CAN module architecture is based around a 16-entry mail-
box RAM. The mailbox is accessed sequentially by the CAN
serial interface or the host CPU. Each mailbox consists of eight
16-bit data words. The data is divided into fields, which includes
a message identifier, a time stamp, a byte count, up to 8 bytes of
data, and several control bits. Each node monitors the messages
being passed on the network. If the identifier in the transmitted
message matches an identifier in one of its mailboxes, then the
module knows that the message was meant for it, passes the data
into its appropriate mailbox, and signals the host of its arrival
with an interrupt.
The CAN network itself is a single, differential pair line. All
nodes continuously monitor this line. There is no clock wire.
Messages are passed in one of four standard message types or
frames. Synchronization is achieved by an elaborate sync
scheme performed in each CAN receiver. Message arbitration is
accomplished one bit at a time. A dominant polarity is estab-
lished for the network. All nodes are allowed to start
transmitting at the same time following a frame sync pulse.
As each node transmits a bit, it checks to see if the bus is the
same state that it transmitted. If it is, it continues to transmit. If
not, then another node has transmitted a dominant bit so the
first node knows it has lost the arbitration and it stops transmit-
ting. The arbitration continues, bit by bit until only one node is
left transmitting.
The electrical characteristics of each network connection are
very stringent so the CAN interface is typically divided into two
parts: a controller and a transceiver. This allows a single con-
troller to support different drivers and CAN networks. The
• SPORT operates at a frequency of up to one-half the clock
• SPORT: Capable of UART software emulation.
• Conforms to the CAN V2.0B standard.
• Supports both standard (11-bit) and extended (29-bit)
• 16 configurable mailboxes (all receive or transmit).
• Dedicated acceptance mask for each mailbox.
• Data filtering (first 2 bytes) which can be used for accep-
• Error status and warning registers.
• Transmit priority by identifier.
• Universal counter module.
• Readable receive and transmit counters.
frequency of the HCLK.
identifiers.
Supports data rates of up to 1 Mbps (and higher).
tance filtering.
Rev. A | Page 9 of 60 | August 2007
ADSP-21992 CAN module represents only the controller part of
the interface. The network I/O of this module is a single trans-
mit line and a single receive line, which communicate to a line
transceiver.
ANALOG-TO-DIGITAL CONVERSION SYSTEM
The ADSP-21992 contains a fast, high accuracy, multiple input
analog-to-digital conversion system with simultaneous sam-
pling capabilities. This analog-to-digital conversion system
permits the fast, accurate conversion of analog signals needed in
high performance embedded systems. Key features of the ADC
system are:
The ADC system is based on a pipeline flash converter core, and
contains dual input sample-and-hold amplifiers so that simulta-
neous sampling of two input signals is supported. The ADC
system provides an analog input voltage range of 2.0 V p-p and
provides 14-bit performance with a clock rate of up to
HCLK
a clock rate from HCLK⁄4 to HCLK⁄30, to a maximum clock rate
of 20 MHz (at 160 MHz CCLK rate).
The ADC input structure supports eight independent analog
inputs; four of which are multiplexed into one sample-and-hold
amplifier (A_SHA) and four of which are multiplexed into the
other sample-and-hold amplifier (B_SHA).
At the 20 MHz sampling rate, the first data value is valid
approximately 375 ns after the convert start command. All eight
channels are converted in approximately 725 ns.
The core of the ADSP-21992 provides 14-bit data such that the
stored data values in the ADC data registers are 14 bits wide.
VOLTAGE REFERENCE
The ADSP-21992 contains an on-board band gap reference that
can be used to provide a precise 1.0 V output for use by the
analog-to-digital system and externally on the VREF pin for
biasing and level shifting functions. Additionally, the ADSP-
21992 may be configured to operate with an external reference
applied to the VREF pin, if required.
• 14-bit pipeline (6-stage pipeline) flash analog-to-digital
• 8 dedicated analog inputs.
• Dual-channel simultaneous sampling capability.
• Programmable ADC clock rate to maximum of HCLK
• First channel ADC data valid approximately 375 ns after
• All 8 inputs converted in approximately 725 ns (at
• 2.0 V peak-to-peak input voltage range.
• Multiple convert start sources.
• Internal or external voltage reference.
• Out of range detection.
• DMA capable transfers from ADC to memory.
converter.
CONVST (at 20 MSPS).
20 MSPS).
4. The ADC system can be programmed to operate at
ADSP-21992
4.