ADSP-2196MKSTZ-160 Analog Devices Inc, ADSP-2196MKSTZ-160 Datasheet
ADSP-2196MKSTZ-160
Specifications of ADSP-2196MKSTZ-160
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ADSP-2196MKSTZ-160 Summary of contents
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... Preliminary Technical Data ADSP-219x DSP CORE FEATURES 6.25 ns Instruction Cycle Time (Internal), for up to 160 MIPS Sustained Performance ADSP-218x Family Code Compatible with the Same Easy -to-Use Algebraic Syntax Single-Cycle Instruction Execution Up to 16M words of Addressable Memory Space with 24 Bits of Addressing Width ...
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... Words of On-Chip RAM, Configured as 8K Words On-Chip 24-bit RAM and 8K Words On-Chip 16-bit RAM 16K Words of On-Chip 24-bit ROM Architecture Enhancements beyond ADSP-218x Family are Supported with Instruction Set Extensions for Added Registers, Ports, and Peripherals Flexible Power Management with Selectable ...
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... September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-219x dSP Core Features . . . . . . . . . . . . . . . . . . . 1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . 1 ADSP-2196 DSP Features . . . . . . . . . . . . . . . . . . . . . 2 General Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DSP Core Architecture . . . . . . . . . . . . . . . . . . . . 4 DSP Peripherals Architecture . . . . . . . . . . . . . . . 5 Memory Architecture . . . . . . . . . . . . . . . . . . . . . 6 Internal (On-Chip) Memory . . . . . . . . . . . . . . . . 6 Internal On-Chip ROM . . . . . . . . . . . . . . . . . . . . 6 On-Chip Memory Security . . . . . . . . . . . . . . . . . 7 External (Off-Chip) Memory . . . . . . . . . . . . . . . . 7 External Memory Space ...
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... The ADSP-2196 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every single-word instruction can be executed in a single processor cycle. The ADSP-2196 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development ...
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... Program memory can store both instructions and data, per- mitting the ADSP-2196 to fetch two operands in a single cycle, one from program memory and one from data memory. The DSP’s dual memory buses also let the ADSP-219x core fetch an operand from data memory and the next instruction from program memory in a single cycle ...
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... These assignments determine the priority of each peripheral for interrupt service. There are three serial ports on the ADSP-2196 that provide a complete synchronous, full-duplex serial interface. This interface includes optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation ...
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... ROM protection is set, the on-chip ROM space cannot be accessed by a hardware emulator. External (Off-Chip) Memory Each of the ADSP-2196’s off-chip memory spaces has a separate control register, so applications can configure unique access parameters for each space. The access param- eters include read and write wait counts, waitstate completion mode, I/O clock divide ratio, write hold time extension, strobe polarity, and data bus width ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Figure 3. ADSP-2196 Memory Map, with On-Chip ROM peripherals can access the DSP’s off-chip boot memory space. After reset, the DSP always starts executing instruc- tions from the on-chip boot ROM. Depending on the boot configuration, the boot ROM code can start booting the DSP from boot memory ...
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... On-chip stacks preserve the processor status and are auto matically maintained during interrupt handling. To support interrupt, loop, and subroutine nesting, the PC stack is 33 levels deep, the loop stack is eight levels deep, and the status stack is 16 levels deep. To prevent stack overflow, the ADSP-2196 Reset ID Priority ...
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... Memory DMA 11—Lowest Host Port The ADSP-2196’s Host port functions as a slave on the external bus of an external Host. The Host port interface lets a Host read from or write to the DSP’s memory space, boot space, or internal I/O space. Examples of Hosts include external microcontrollers, microprocessors, or ASICs ...
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... Otherwise, the Host port interface asserts ACK when it has completed the memory access successfully. DSP Serial Ports (SPORTs) The ADSP-2196 incorporates three complete synchronous serial ports (SPORT0, SPORT1, and SPORT2) for serial and multiprocessor communications. The SPORTs support the following features: ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Serial Peripheral Interface (SPI) Ports The DSP has two SPI-compatible ports that enable the DSP to communicate with multiple SPI-compatible devices. These ports are multiplexed with SPORT2, so either SPORT2 or the SPI ports are active, depending on the state of the OPMODE pin during hardware reset ...
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... Power-Down Core • Power-Down Core/Peripherals • Power-Down All Idle Mode When the ADSP-2196 is in Idle mode, the DSP core stops executing instructions, retains the contents of the instruc- tion pipeline, and waits for an interrupt. The core clock and peripheral clock continue running. ...
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... PLL) resumes executing instructions with the instruc- tion after the IDLE. Clock Signals The ADSP-2196 can be clocked by a crystal oscillator or a buffered, shaped clock derived from an external clock oscil- lator crystal oscillator is used, the crystal should be connected across the CLKIN and XTAL pins, with two ...
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... Program control jumps to the location of the on-chip boot ROM (0xFF0000). Power Supplies The ADSP-2196 has separate power supply connections for the internal (V ) and external (V DDINT DDEXT The internal supply must meet the 2 ...
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... Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. September 2001 The ADSP-2196 asserts the BGH pin when it is ready to start another external port access, but is held off because the bus was previously granted. This mechanism can be extended to define more complex arbitration protocols for implementing more elaborate multimaster systems ...
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... Maintain a one-to-one correspondence with the tool’s command line switches. Analog Devices’ DSP emulators use the IEEE 1149.1 JTAG test access port of the ADSP-2196 processor to monitor and control the target board processor during emulation. The emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks ...
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... ADSP-219x/2191 DSP Hardware Reference. PIN DESCRIPTIONS ADSP-2196 pin definitions are listed in ADSP-2196 inputs are asynchronous and can be asserted asynchronously to CLKIN (or to TCK for TRST). Unused inputs should be tied or pulled to V except for ADDR21–0, DATA15–0, PF7-0, and inputs that ...
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... Programmable Flags 3/SPI1 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 3 /SPI1SEL1 I (during boot) /MSEL3 I REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. ADSP-2196 19 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Table 7. Pin Descriptions (Continued) Pin Type Function PF2 I/O/T Programmable Flags 2/SPI0 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 2 /SPI0SEL1 I (during boot) /MSEL2 I PF1 I/O/T Programmable Flags 1/SPI1 Slave Select input (when SPI1 enabled)/Multiplier Select 1 ...
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... Test Data Output (JTAG). Serial scan output of the boundary scan path. TRST I Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-2196. The TRST pin has internal pull-down resistor. EMU O Emulation Status (JTAG) ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS 1 Parameter Description V Internal (Core) Supply Voltage DDINT V External (I/O) Supply Voltage DDEXT V High Level Input Voltage IH1 V High Level Input Voltage IH2 V Low Level Input Voltage IL T Ambient Operating Temperature ...
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... Disabled HCLK = 80 MHz, CCLK = 160 7,8 MHz HCLK = 80 MHz, CCLK = 160 7,8 MHz PLL Enabled, Core, HCLK Disabled HCLK = 80 MHz PLL, Core, HCLK, CLKIN Disabled MHz 25°C, CASE ADSP-2196 Min Typical Max Unit 1 mA 184 mA 215 100 µA 7 TBD pF 23 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2196 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid perfor- mance degradation or loss of functionality ...
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... MSELx/BYPASS stable before RESET asserted setup MSLS t MSELx/BYPASS stable after RESET de-asserted hold MSLH 1 Figure 11 shows a 2 ratio between CLKOUT = 2 CLKIN (or t see the System Design chapter of the ADSP-219x/2191 DSP Hardware Reference clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN=CCLK bypass mode CCLK REV ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Programmable Flags Cycle Timing Table 9 and Figure 12 describe programmable flag operations. Table 9. Programmable Flags Cycle Timing Parameter Description Switching Characteristic t Flag output delay with respect to HCLK DFO t Flag output hold after HCLK high ...
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... This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. Min 1 6.25 32 equals (2 –1) cycles. HTO Figure 13. Timer PWM_OUT Cycle Timing ADSP-2196 Max Unit 32 (2 –1) cycles ns 27 ...
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... ACK. To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP to wait, and the DSP requires two EMI clock cycles after ACK goes high to finish the access. For more information, see the External Port chapter in the ADSP-219x/2191 DSP Hardware Reference Table 11. External Port Write Cycle Timing ...
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... For current information contact Analog Devices at 800/262-5643 REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. Figure 14. External Port Write Cycle Timing ADSP-2196 29 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 External Port Read Cycle Timing Table 12 and Figure 15 describe external port read operations. For additional information on the ACK signal, see the discussion on on page 28. Table 12. External Port Read Cycle Timing Parameter Description Switching Characteristics ...
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... For current information contact Analog Devices at 800/262-5643 REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. Figure 15. External Port Read Cycle Timing ADSP-2196 31 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 External Port Bus Request and Grant Cycle Timing Table 13 and Figure 16 describe external port bus request and bus grant operations. Table 13. External Port Bus Request and Grant Cycle Timing Parameter Description Switching Characteristics ...
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... Figure 16. External Port Bus Request and Grant Cycle Timing REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. ADSP-2196 33 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Host Port ALE Mode Write Cycle Timing Table 14 and Figure 17 describe host port write operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description Table 14 ...
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... For current information contact Analog Devices at 800/262-5643 REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. Figure 17. Host Port ALE Mode Write Cycle Timing ADSP-2196 35 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Host Port ACC Mode Write Cycle Timing Table 15 and Figure 18 describe host port write operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description Table 15 ...
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... For current information contact Analog Devices at 800/262-5643 REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. Figure 18. Host Port ACC Mode Write Cycle Timing ADSP-2196 37 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Host Port ALE Mode Read Cycle Timing Table 16 and Figure 19 describe host port read operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description Table 16 ...
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... For current information contact Analog Devices at 800/262-5643 REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. Figure 19. Host Port ALE Mode Read Cycle TIming ADSP-2196 39 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Host Port ACC Mode Read Cycle Timing Table 17 and Figure 20 describe host port read operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description Table 17 ...
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... For current information contact Analog Devices at 800/262-5643 REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. Figure 20. Host Port ACC Mode Read Cycle TIming ADSP-2196 41 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Serial Port (SPORT) Clocks and Data Timing Table 18 and Figure 21 describe SPORT transmit and receive operations. Table 18. Serial Port (SPORT) Clocks and Data Timing Parameter Description Switching Characteristics t RFS Hold after RCLK (Internally Generated RFS) ...
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... For current information contact Analog Devices at 800/262-5643 REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. Figure 21. Serial Port (SPORT) Clocks and Data ADSP-2196 43 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Serial Port (SPORT) Frame Synch Timing Table 19 and Figure 22 describe SPORT frame synch operations. To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) R/TCLK width ...
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... For current information contact Analog Devices at 800/262-5643 REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. Figure 22. Serial Port (SPORT) Frame Synch ADSP-2196 45 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Serial Peripheral Interface (SPI) Port—Master Timing Table 20 and Figure 23 describe SPI port master operations. Table 20. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Description Switching Characteristics t SPIxSEL low to first SCLK edge (x SDSCIM ...
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... For current information contact Analog Devices at 800/262-5643 Figure 23. Serial Peripheral Interface (SPI) Port—Master REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. ADSP-2196 47 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Serial Peripheral Interface (SPI) Port—Slave Timing Table 21 and Figure 24 describe SPI port slave operations. Table 21. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Description Switching Characteristics t SPISS assertion to data out active DSOE ...
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... For current information contact Analog Devices at 800/262-5643 REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. Figure 24. Serial Peripheral Interface (SPI) Port—Slave ADSP-2196 49 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure 25 describes UART port receive and transmit oper- ations. The maximum baud rate is HCLK/16. As shown in Figure 25 there is some latency between the generation 50 This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice ...
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... This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. JTAG Test And Emulation Port Timing Table 22 and Figure 26 describe JTAG port operations. Min Figure 26. JTAG Port Timing ADSP-2196 Max Unit ...
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... For current information contact Analog Devices at 800/262-5643 Output Drive Currents Figure 27 shows typical I-V characteristics for the output drivers of the ADSP-2196. The curves represent the current drive capability of the output drivers as a function of output voltage. Power Dissipation Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers ...
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... The bus cycle time is 100 MHz (t HCLK REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing but selects CK with EXT = 20 nsec) ADSP-2196 53 ...
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... Figure 31. trip point, as shown in the Output Enable/Disable diagram (Figure 32). If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. ADSP-2196 EXT 10.9 V =TBD W 10.9 V =TBD W 10 ...
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... DSP is operating (as close as possible to the influence performance. thermal pathways) with a thermal adhesive. Thermal Characteristics Where: The ADSP-2196 comes in a 144-lead LQFP or 144-lead • T AMB Ball Grid Array (mini-BGA) ture (measured near top package. The ADSP-2196 is surface of package) specified for an ambient tem- • ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Figure 36. Typical Output Rise Time (10%-90%, V =Min) vs. Load Capacitance DDEXT Figure 37. Typical Output Delay or Hold vs. Load Capacitance (at Max Case Temperature) = – AMB CASE Figure 38. T Calculation CASE 1 Table 25. Values CA Airflow 0 100 (Linear Ft./Min.) ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 1 These are preliminary estimates. 57 This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Table 26. 144-Lead LQFP ADSP-2196 144-Lead LQFP Pins (Alphabetically By Pinout Signal) (Continued) Table 26 lists the LQFP pinout by signal name. SIGNAL Table 26. 144-Lead LQFP BMODE1 Pins (Alphabetically By BMS Signal) BR SIGNAL PIN # BYPASS A0 84 CLKOUT A1 85 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Table 27 Table 26. 144-Lead LQFP Pins (Alphabetically By pinout by pin number. Signal) (Continued) Table 27. 144-Lead LQFP Pins (Numerically By Pin SIGNAL PIN # Number TRST 79 SIGNAL TXD 53 D14 V 13 DDEXT D15 V 25 DDEXT HAD0 V 40 DDEXT HAD1 ...
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... ADSP-2196 For current information contact Analog Devices at 800/262-5643 Table 27. 144-Lead LQFP Pins (Numerically By Pin Number (Continued) SIGNAL PIN # DDEXT GND A10 96 A11 97 A12 98 A13 99 V 100 DDEXT A14 101 A15 102 A16 103 A17 104 GND 105 A18 106 A19 107 ...
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... D11 141 D12 142 V 143 DDEXT D13 144 REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. ADSP-2196 61 ...
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... September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-2196 144-Lead Mini-BGA Pinout Table 28 lists the mini-BGA pinout by signal name. Table 28. 144-Lead Mini-BGA Pins (Alphabetically By Signal) SIGNAL BALL # A0 J11 H10 A3 G12 A4 H11 A5 G10 A6 F12 A7 G11 A8 F10 A9 F11 A10 E12 A11 E11 ...
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... Signal) (Continued) SIGNAL BALL # PF2 M2 PF3 L2 PF4 M3 PF5 L3 PF6 K3 PF7 M4 RCLK0 K7 RCLK1 J9 RCLK2 RESET L12 RFS0 K8 RFS1 M10 RFS2 M6 RXD K6 TCK K11 DT0 H6 TCLK1 M9 TCLK2 K5 TDI K12 TDO L11 TFS0 M8 TFS1 J8 TFS2 M5 TMR0 K4 TMR1 L4 TMR2 J4 TMS K10 TRST J12 TXD M7 ADSP-2196 63 ...
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... Table 29. 144-Lead Mini-BGA Pins (Numerically By Ball Number) SIGNAL BALL # GND A1 D13 CLKIN ACK A8 MS1 A9 BMS A10 A21 A11 GND A12 D14 B1 D15 B2 HAD1 B3 D11 XTAL BGH B10 A20 B11 A19 B12 HAD0 C1 HAD2 C2 D12 C3 D10 ADSP-2196 64 ...
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... Ball Number) (Continued) SIGNAL BALL # A10 E12 HAD10 F1 HAD12 F2 HAD14 DDINT V F5 DDEXT V F6 DDEXT GND F7 GND F8 GND F9 A8 F10 A9 F11 A6 F12 HACK_P G1 HAD13 G2 HAD15 G3 GND G4 GND G5 GND DDEXT V G8 DDEXT V G9 DDINT A5 G10 A7 G11 A3 G12 HCMS H1 HA16 H2 HACK H3 DT2 H4 GND H5 ADSP-2196 65 ...
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... Table 29. 144-Lead Mini-BGA Pins (Numerically By Ball Number) (Continued) SIGNAL BALL # TDI K12 PF1 L1 PF3 L2 PF5 L3 TMR1 L4 DR2 L5 GND L6 DR0 L7 DT1 L8 BMODE1 L9 BMODE0 L10 TDO L11 RESET L12 GND M1 PF2 M2 PF4 M3 PF7 M4 TFS2 M5 RFS2 M6 TXD M7 TFS0 M8 TCLK1 M9 RFS1 M10 BYPASS M11 GND M12 ADSP-2196 66 ...
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... METRIC THIN PLASTIC QUAD FLATPACK (LQFP) (ST-144) REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. OUTLINE DIMENSIONS 144-BALL MINI-BGA (CA-144) ADSP-2196 67 ...
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... September 2001 For current information contact Analog Devices at 800/262-5643 1, 2 Part Number Ambient Temperature Range Instruction Rate On-Chip SRAM ADSP-2196MKST -160X 0ºC to 70ºC ADSP-2196MBST -140X -40ºC to 85ºC ADSP-2196MKCA-160X 0ºC to 70ºC ADSP-2196MBCA-140X -40ºC to 85º Plastic Thin Quad Flatpack (LQFP). ...