ADSP-2196MKSTZ-160 Analog Devices Inc, ADSP-2196MKSTZ-160 Datasheet - Page 42

• Manufacturer Part Number: ADSP-2196MKSTZ-160
• Description: IC DSP CONTROLLER 16BIT 144-LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2196MKSTZ-160

• Interface: Host Interface, SPI, SSP, UART
• Clock Rate: 160MHz
• Non-volatile Memory: ROM (48 kB)
• On-chip Ram: 40kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 160MHz
• Mips: 160
• Device Input Clock Speed: 160MHz
• Ram Size: 40KB
• Program Memory Size: 48KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37V
• Operating Supply Voltage (max): 2.63/3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-2196
Serial Port (SPORT) Clocks and Data Timing
Table 18
Table 18. Serial Port (SPORT) Clocks and Data Timing
1
2
3
4
42
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed:
1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
Referenced to drive edge.
Referenced to sample edge.
RFS hold after RCLK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCLK for late external TFS is 0 ns minimum from
drive edge.
Parameter
Switching Characteristics
t
t
t
t
t
t
Timing Requirements
t
t
t
t
t
t
t
t
t
t
HOFSE
DFSE
DDTEN
DDTTE
DDTIN
DDTTI
SCLKIW
SFSI
HFSI
SDRI
HDRI
SCLKW
SFSE
HFSE
SDRE
HDRE
and
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
Figure 21
Description
RFS Hold after RCLK (Internally Generated RFS)
RFS Delay after RCLK (Internally Generated RFS)
Transmit Data Delay after TCLK
Data Disable from External TCLK
Data Enable from Internal TCLK
Data Disable from Internal TCLK
TCLK/RCLK Width
TFS/RFS Setup before TCLK/RCLK
TFS/RFS Hold after TCLK/RCLK
Receive Data Setup before RCLK
Receive Data Hold after RCLK
TCLK/RCLK Width
TFS/RFS Setup before TCLK/RCLK
TFS/RFS Hold after TCLK/RCLK
Receive Data Setup before RCLK
Receive Data Hold after RCLK
describe SPORT transmit and receive operations.
For current information contact Analog Devices at 800/262-5643
3
3
2
3
3
2
2
2
3, 4
3, 4
3
3
1
2
2
Min
0
0
0
0
0
0
20
–0.6
–0.3
–2.3
1.9
20
–0.6
–0.6
–2.2
1.8
September 2001
Max
12.4
12.4
12.1
12.0
6.8
6.3
REV. PrA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns