ADMCF326BR Analog Devices Inc, ADMCF326BR Datasheet
ADMCF326BR
Specifications of ADMCF326BR
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ADMCF326BR Summary of contents
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TARGET APPLICATIONS Washing Machines, Refrigerator Compressors, Fans, Pumps, Industrial Variable Speed Drives MOTOR TYPES AC Induction Motors Permanent Magnet Synchronous Motors (PMSM) Brushless DC Motors (BDCM) FEATURES 20 MIPS Fixed-Point DSP Core Single Cycle Instruction Execution (50 ns) ADSP-21xx ...
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ADMCF326–SPECIFICATIONS ANALOG-TO-DIGITAL CONVERTER Parameter Signal Input 1 Resolution 2 Linearity Error 2 Zero Offset Channel-to-Channel Comparator Match Comparator Delay 2 ADC High Level Input Current 2 ADC Low Level Input Current NOTES 1 Resolution varies with PWM switching frequency (double ...
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VOLTAGE REFERENCE Parameter Voltage Level (V ) REF Output Voltage Drift Specifications subject to change without notice. POWER-ON RESET Parameter Reset Threshold (V ) RST Hysteresis (V ) HYST t Reset Active Timeout Period ( ) RST * 16 2 ...
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ADMCF326 TIMING PARAMETERS Parameter Clock Signals Signal t is defined as 0 The ADMCF326 uses an input clock with a CK CKIN frequency equal to half the instruction rate MHz input clock (equivalent to 100 ns) ...
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Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High to ...
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... Temperature Model Range ADMCF326BR –40°C to +85°C ADMCF326BN –40°C to +85°C ADMCF326-EVALKIT CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMCF326 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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GENERAL DESCRIPTION The ADMCF326 is a low cost, single-chip DSP-based controller, suitable for permanent magnet synchronous motors, ac induction motors, and brushless dc motors. The ADMCF326 integrates a 20 MIPS, fixed-point DSP core with a complete set of motor control ...
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ADMCF326 DSP CORE ARCHITECTURE OVERVIEW Figure overall block diagram of the DSP core of the ADMCF326, which is based on the fixed-point ADSP-2171. The flexible architecture and comprehensive instruction set of the ADSP-2171 allow the processor to ...
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Serial Port The ADMCF326 incorporates a complete synchronous serial port (SPORT1) for serial communication and multiprocessor com- munication. The following is a brief list of capabilities of the ADMCF326 SPORT1. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for ...
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ADMCF326 FLASH MEMORY SUBSYSTEM The ADMCF326 has 4K × 24-bit of user-programmable, non- volatile flash memory. A flash programming utility is provided with the development tools, which performs the basic device programming operations: erase, program, and verify. The flash memory ...
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V RST RST RESET Figure 5. Power-On Reset Operation The ADMCF326 reset sets all internal stack pointers to the empty stack condition, masks all interrupts, clears the MSTAT Register and performs a full reset of all of ...
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ADMCF326 A functional block diagram of the PWM controller is shown in Figure 6. The generation of the six output PWM signals on pins controlled by four important blocks: • The three-phase PWM timing unit, which ...
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For example, for a 20 MHz CLKOUT and a desired PWM = 100 µs), the correct value switching frequency of 10 kHz ( load into the PWMTM Register is: × PWMTM 1000 × × ...
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ADMCF326 over half the PWM period. The switching signals produced by the three-phase timing unit are also adjusted to incorporate the programmed dead time value in the PWMDT Register. The PWM is center-based. This means that in Single Update Mode ...
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Writing to these registers also starts the main PWM timer. If during initialization, the PWMTM Register is written before the PWMCHA, PWMCHB, and PWMCHC Registers, the first PWMSYNC pulse (and interrupt if enabled) will be gener- ated (1.5 ...
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ADMCF326 same time. In the control of an ECM, one inverter leg (Phase C in this example) is disabled for a number of PWM cycles. This disable may be implemented by disabling both the CH and CL PWM outputs by ...
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Table V. Fundamental Characteristics of PWM Generation Unit of ADMCF326 16-BIT PWM TIMER Parameter Counter Resolution Edge Resolution (Single Update Mode) Edge Resolution (Double Update Mode) Programmable Dead Time Range Programmable Dead Time Increments Programmable Pulse Deletion Range Programmable Pulse ...
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ADMCF326 VIL t VIL T –T PWM CRST PWMSYNC COMPARATOR OUTPUT Figure 12. Analog Input Block Operation The ADC system consists of four comparators and a single timer, which may be clocked at either the DSP rate ...
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ADC Reference Ramp Calibration The peak of the ADC ramp voltage should be as close as possible to 3 achieve the optimum ADC resolution and signal range. When the current source is in the default state, the peak ...
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ADMCF326 By default following a reset, Bit 8 of the MODECTRL Register is cleared, thus enabling Offset Mode. In addition, the registers AUXTM0 and AUXTM1 default to 0xFF, corresponding to the minimum switching frequency and zero offset. The on-time registers ...
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AUXILIARY PWM TIMERS Parameter Resolution PWM Frequency Following power-on or reset, all bits of PIOINTEN0 and PIOINTEN1 are cleared so that no interrupts are enabled. Each PIO line has an internal pull-down resistor so that follow- ing power-on or reset, ...
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ADMCF326 Bit 2 is used to configure the IRQ2 interrupt recommended that the IRQ2 interrupt always be configured as level-sensitive to ensure that no peripheral interrupts are lost. Setting Bit 4 of the ICNTL Register enables interrupt nesting. ...
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Address (HEX) Name 0x2000 ADC1 0x2001 ADC2 0x2002 ADC3 0x2003 ADCAUX 0x2004 PIODIR0 0x2005 PIODATA0 0x2006 PIOINTEN0 0x2007 PIOFLAG0 0x2008 PWMTM 0x2009 PWMDT 0x200A PWMPD 0x200B PWMGATE 0x200C PWMCHA 0x200D PWMCHB 0x200E PWMCHC 0x200F PWMSEG 0x2010 AUXCH0 0x2011 AUXCH1 0x2012 ...
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ADMCF326 Address Name 0x3FFF SYSCNTL 0x3FFE MEMWAIT 0x3FFD TPERIOD 0x3FFC TCOUNT 0x3FFB TSCALE 0x3FFA . . . F3 0x3FF2 SPORT1_CTRL_REG 0x3FF1 SPORT1_SCLKDIV 0x3FF0 SPORT1_RFSDIV 0x3FEF SPORT1_AUTOBUF_CTRL Table XI. DSP Core Registers Bits [ [ ...
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BOOT–FROM–FLASH–CODE RESERVED ALWAYS READ 0 Figure 19. Configuration of Flash Memory Registers Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always ...
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ADMCF326 CHANNEL CROSSOVER CROSSOVER B CHANNEL CROSSOVER 1 = CROSSOVER C CHANNEL CROSSOVER Default bit values are ...
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LOW SIDE GATE CHOPPING 0 = DISABLE 1 = ENABLE HIGH SIDE GATE CHOPPING Figure 21. Configuration of Additional ...
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ADMCF326 ...
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Figure 23. Configuration of Additional PIO Registers Default bit values are shown value is ...
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ADMCF326 Default bit values are shown ...
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Figure 25. Configuration of Additional AUX Registers Default bit values are shown value is shown, the bit field is undefined at ...
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ADMCF326 OFFSET MODE AUXILIARY 1 = INDEPENDENT MODE PWM SELECT ADC 0 = CLKIN RATE COUNTER 1 = CLKOUT RATE SELECT 1ST HALF OF ...
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DISABLE 1 = ENABLE 15 0 INTERRUPT FORCE IRQ2 SOFTWARE 1 SOFTWARE 0 SPORT1 TRANSMIT OR IRQ1 SPORT1 RECEIVE OR IRQ0 TIMER PERIPHERAL (OR IRQ2 DISABLE (MASK) 1 ...
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ADMCF326 0 = DISABLED SPORT1 ENABLE 1 = ENABLED THE ROM MONITOR WRITES 0x8000 TO THIS REGISTER SYSCNTL (R/ ...
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COPLANARITY 0.10 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-013AE PIN 1 6.35 (0.2500) MAX ...
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