ADMCF327BR Analog Devices Inc, ADMCF327BR Datasheet - Page 32

IC DSP SW MOTOR CTRLR 28SOIC

ADMCF327BR

Manufacturer Part Number
ADMCF327BR
Description
IC DSP SW MOTOR CTRLR 28SOIC
Manufacturer
Analog Devices Inc
Series
Motor Controlr
Type
Fixed Pointr
Datasheet

Specifications of ADMCF327BR

Rohs Status
RoHS non-compliant
Interface
Synchronous Serial Port (SSP)
Clock Rate
20MHz
Non-volatile Memory
FLASH (12 kB), ROM (12kB)
On-chip Ram
2.5kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / Rohs Status
Not Compliant
ADMCF327
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
1 = INDEPENDENT MODE
1 = CLKOUT RATE
0 = OFFSET MODE
0 = CLKIN RATE
0 = 1ST HALF OF PWM
1 = 2ND HALF OF PWM
CYCLE
CYCLE
15
15
15
0
0
0
14
14
14
0
0
0
PWM SELECT
AUXILIARY
COUNTER
15
SELECT
0
13
13
13
ADC
0
0
0
14
0
12
12
12
0
0
0
13
PWM TIMER
0
11
11
11
0
STATUS
0
0
12
0
10
10
10
0
0
0
11
0
9
0
0
9
WDTIMER (W)
9
0
SYSSTAT (R)
IRQFLAG (R)
10
0
8
0
8
8
0
0
MODECTRL (R/W)
9
0
7
0
0
0
7
7
8
0
6
0
0
6
6
0
7
0
5
0
0
0
5
5
6
0
0
0
0
4
4
4
5
0
0
3
0
3
3
0
4
1
2
2
0
2
0
0
3
1
1
0
1
0
2
0
0
0
0
0
0
1
0
PIN STATUS
WATCHDOG
RECEIVE SELECT
DM (0x2016)
PWMTRIP INTERRUPT
PWMSYNC INTERRUPT
DM (0x2018)
PWMTRIP
MODE SELECT
SPORT1 MODE
DM (0x2017)
SPORT1 DATA
PWM UPDATE
STATUS
INTERRUPT
INTERRUPT
PWMSYNC
PWMTRIP
0
0
SELECT
DM (0x2015)
ADC MUX CONTROL
00 VAUX0
01 VAUX1
10 VAUX2
11 VAUX3
0 = LOW
1 = HIGH
0 = NORMAL
1 = WATCHDOG RESET
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DR1A
1 = DR1B
0 = SPORT
1 = UART
0 = SINGLE UPDATE MODE
1 = DOUBLE UPDATE MODE
OCCURRED
0 = NO INTERRUPT
1 = INTERRUPT
OCCURRED

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