ADSP-2181KS-115 Analog Devices Inc, ADSP-2181KS-115 Datasheet - Page 16
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ADSP-2181KS-115
Manufacturer Part Number
ADSP-2181KS-115
Description
IC DSP CONTROLLER 16BIT 128PQFP
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet
1.ADSP-2181BSZ-133.pdf
(32 pages)
Specifications of ADSP-2181KS-115
Rohs Status
RoHS non-compliant
Interface
Synchronous Serial Port (SSP)
Clock Rate
28.8MHz
Non-volatile Memory
External
On-chip Ram
80kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
ADSP-2181
Parameter
Bus Request/Grant
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
2
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
BH
BS
SD
SDB
SE
SEC
SDBH
SEH
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships.
BR Hold after CLKOUT High
BR Setup before CLKOUT Low
CLKOUT High to xMS,
RD, WR Disable
xMS, RD, WR
Disable to BG Low
BG High to xMS,
RD, WR Enable
xMS, RD, WR
Enable to CLKOUT High
xMS, RD, WR
Disable to BGH Low
BGH High to xMS,
RD, WR Enable
PMS, DMS
CLKOUT
CLKOUT
BMS, RD
BGH
WR
BR
BG
2
2
t
Figure 10. Bus Request–Bus Grant
SD
t
1
BH
1
t
t
BS
t
SDBH
SDB
–16–
Min
0.25t
0.25t
0
0
0.25t
0
0
CK
CK
CK
+ 2
+ 17
– 4
t
t
SEH
SE
t
SEC
Max
0.25t
CK
+ 10
REV. D
Unit
ns
ns
ns
ns
ns
ns
ns
ns