EP3C5F256C8N Altera, EP3C5F256C8N Datasheet

IC CYCLONE III FPGA 5K 256-FBGA

EP3C5F256C8N

Manufacturer Part Number
EP3C5F256C8N
Description
IC CYCLONE III FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C5F256C8N

Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
321
Family Type
Cyclone III
No. Of I/o's
182
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2423
EP3C5F256C8N

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Table 1. Cyclone III Device Family Issues
M9K Memory Block Read Issue
© June 2010 Altera Corporation
ES-01020-3.0
M9K Memory Block Read Issue
External Memory Specification for DDR2 SDRAM Full
Rate on the Column I/O
MSEL pins may be sensed at a different setting than was
intended if connected to V
sags below 0.75 after power on reset and before
configuration starts.
Momentary current surge from the V
configuration.
© June 2010
This errata sheet provides updated technical information for Cyclone
This document addresses known device issues and includes methods to work around
the issues.
Table 1
The Cyclone III M9K embedded memory blocks may exhibit bit error in which the
read bit is a 1 when the expected bit is a 0. The problem is caused by bitline coupling
in the read output. The issue is rare and requires the presence of multiple conditions
for the M9K block to be susceptible to the bit error. The conditions include the use
model of the M9K block, the application data pattern, and the operating conditions.
Designs using the M9K blocks in dual clock and widest data width (×32 or ×36)
modes are most susceptible to the bit error. Designs using the M9K blocks in single
clock or narrower data width modes are not affected when operating within data
sheet specifications. The problem is highly data-pattern dependent and triggered by
specific data bit combinations. Lastly, the problem can be exacerbated by lower
temperature and lower voltage operations. The presence of all these conditions does
not imply a bit error would necessarily occur. In addition, if some or all of the
conditions are not present, the error will not occur.
Issue
CCIO
for logic high and V
lists the specific issues and which Cyclone III devices each issue affects.
CCINT
supply after
CCIO
All 65-nm and some 60-nm
Cyclone III and Cyclone III LS
devices. For more information,
refer to
All Cyclone III devices
All Cyclone II devices
EP3C25 ES Revision B and C
EP3C120 ES Revision A
Affected Devices
Table
2.
Cyclone III Device Family
For a solution, refer to
Memory Block Read
Fixed in:
Cyclone III 60-nm: EP3C55,
EP3C80, and EP3C120 devices,
Revision B
Cyclone III LS: EP3CLS150 and
EP3CLS200 devices,
Revision B
For a solution, refer to
Memory Specification for
DDR2
For a solution, refer to
Pin
Fixed in:
EP3C25 Revision D
EP3C120 Revision B
EP3C120 Revision C
Cyclone III Device Family Errata Sheet
Connection.
SDRAM.
Errata Sheet
Solution
®
III devices.
Issue.
Errata Sheet
External
M9K
MSEL

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EP3C5F256C8N Summary of contents

Page 1

... The presence of all these conditions does not imply a bit error would necessarily occur. In addition, if some or all of the conditions are not present, the error will not occur. © June 2010 Altera Corporation ES-01020-3.0 Cyclone III Device Family ...

Page 2

... Table 2 lists the devices affected by the M9K memory read issue. Figure 1. Altera Data Code Marking Format Table 2. Affected Devices Device Cyclone III 65-nm: All devices ...

Page 3

... Class II I/O standard. (2) You must use a 200-MHz memory component speed grade. MSEL Pin Connection Altera has identified an issue with Cyclone III MSEL pins connected to V high CCIO the MSEL pins may be sensed at a different setting than was intended. The device might then require a power cycle to recover ...

Page 4

... I/O Power Static Current Issue Altera has identified an issue with static current in I/O banks powered at 3.3 Cyclone III EP3C25 Revision B and C and EP3C120 Revision A and B engineering sample devices. The affected devices might draw more current than expected as ...

Page 5

... Altera's standard warranty, San Jose, CA 95134 but reserves the right to make changes to any products and services at any time without notice. Altera assumes no www.altera.com responsibility or liability arising out of the application or use of any information, product, or service Technical Support described herein except as expressly agreed to in writing by Altera Corporation ...

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