EP2C8T144I8N Altera, EP2C8T144I8N Datasheet - Page 87
![IC CYCLONE II FPGA 8K 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EP2C8T144I8N
Manufacturer Part Number
EP2C8T144I8N
Description
IC CYCLONE II FPGA 8K 144-TQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C8T144I8N
Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
85
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
85
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2157
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C8T144I8N
Manufacturer:
ALTERA31
Quantity:
387
Part Number:
EP2C8T144I8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Power-On Reset
Circuitry
Altera Corporation
February 2007
Figure 4–2. Transistor Level Diagram of FPGA Device I/O Buffers
Notes to
(1)
(2)
Cyclone II devices contain POR circuitry to keep the device in a reset state
until the power supply voltage levels have stabilized during power-up.
The POR circuit monitors the V
I/O pins until the V
addition, the POR circuitry also monitors the V
banks that contains configuration pins (I/O banks 1 and 3 for EP2C5 and
EP2C8, I/O banks 2 and 6 for EP2C15A, EP2C20, EP2C35, EP2C50, and
EP2C70) and tri-states all user I/O pins until the V
recommended operating levels.
After the Cyclone II device enters user mode, the POR circuit continues to
monitor the V
user mode can be detected. If the V
point during user mode, the POR circuit resets the device. If the V
voltage sags during user mode, the POR circuit does not reset the device.
"Wake-up" Time for Cyclone II Devices
In some applications, it may be necessary for a device to wake up very
quickly in order to begin operation. The Cyclone II device family offers
the Fast-On feature to support fast wake-up time applications. Devices
that support the Fast-On feature are designated with an “A” in the
ordering code and have stricter power up requirements compared to non-
A devices.
This is the logic array signal or the larger of either the V
This is the larger of either the V
Figure
n+
CCINT
4–2:
Logic Array
p-well
Signal
voltage level so that a brown-out condition during
CC
reaches the recommended operating levels. In
n+
CCIO
V
CCINT
PAD
or V
CCINT
Cyclone II Device Handbook, Volume 1
voltage levels and tri-states all user
PAD
p+
voltage sags below the POR trip
Hot Socketing & Power-On Reset
signal.
(1)
CCIO
CC
CCIO
n-well
level of the two I/O
V
CCIO
p+
reaches the
or V
PAD
(2)
n+
signal.
p-substrate
CCIO
4–5