EP2C8Q208C7N Altera, EP2C8Q208C7N Datasheet - Page 156
![IC CYCLONE II FPGA 8K 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EP2C8Q208C7N
Manufacturer Part Number
EP2C8Q208C7N
Description
IC CYCLONE II FPGA 8K 208-PQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C8Q208C7N
Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
138
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
138
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1672
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C8Q208C7N
Manufacturer:
ALTERA
Quantity:
8
Part Number:
EP2C8Q208C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Timing Specifications
5–66
Cyclone II Device Handbook, Volume 1
f
f
f
t
f
clock output)
f
t
t
t
t
I N
I N P F D
I N D U T Y
I N J I T T E R
O U T _ E X T
O U T
O U T D U T Y
J I T T E R
L O C K
PLL_PSERR
Table 5–54. PLL Specifications
(to global clock)
(p-p)
Symbol
(5)
(external
(2)
Input clock frequency (–6 speed grade)
Input clock frequency (–7 speed grade)
Input clock frequency (–8 speed grade)
PFD input frequency (–6 speed grade)
PFD input frequency (–7 speed grade)
PFD input frequency (–8 speed grade)
Input clock duty cycle
Input clock period jitter
PLL output frequency (–6 speed grade)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
PLL output frequency (–6 speed grade)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
Duty cycle for external clock output (when
set to 50%)
Period jitter for external clock output
f
f
Time required to lock from end of device
configuration
Accuracy of PLL phase shift
O U T _ E X T
O U T _ E X T
PLL Timing Specifications
Table 5–54
the commercial junction temperature range (0° to 85° C), the industrial
junction temperature range (–40° to 100° C), the automotive junction
temperature range (–40° to 125° C), and the extended temperature range
(–40° to 125° C). Follow the PLL specifications for –8 speed grade devices
when operating in the industrial, automotive, or extended temperature
range.
Note (1)
> 100 MHz
≤ 100 MHz
Parameter
describes the Cyclone II PLL specifications when operating in
(Part 1 of 2)
Min
10
10
10
10
10
10
40
10
10
10
10
10
10
45
—
—
—
—
—
200
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Altera Corporation
100
402.5
402.5
402.5
402.5
Max
500
450
±60
300
(4)
(4)
(4)
60
(4)
(4)
(4)
55
30
—
February 2008
(6)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
mUI
ps
ps
μs
ps
%
%