EP1C4F324C6 Altera, EP1C4F324C6 Datasheet - Page 27
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EP1C4F324C6
Manufacturer Part Number
EP1C4F324C6
Description
IC CYCLONE FPGA 4K LE 324-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C4F324C6
Number Of Logic Elements/cells
4000
Number Of Labs/clbs
400
Total Ram Bits
78336
Number Of I /o
249
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1042
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C4F324C6
Manufacturer:
ALTERA
Quantity:
3
Part Number:
EP1C4F324C6
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1C4F324C6N
Manufacturer:
ALTERA
Quantity:
5 510
Company:
Part Number:
EP1C4F324C6N
Manufacturer:
ALTERA
Quantity:
250
Part Number:
EP1C4F324C6N
Manufacturer:
ALTERA
Quantity:
20 000
Figure 2–14. Shift Register Memory Configuration
Altera Corporation
May 2008
w
w
w
w
w × m × n Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
register outputs (number of taps n × width w) must be less than the
maximum data width of the M4K RAM block (×36). To create larger shift
registers, multiple memory blocks are cascaded together.
Data is written into each address location at the falling edge of the clock
and read from the address at the rising edge of the clock. The shift register
mode logic automatically controls the positive and negative edge
clocking to shift the data in one clock cycle.
memory block in the shift register mode.
Memory Configuration Sizes
The memory address depths and output widths can be configured as
4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or 256 × 18
bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit configuration
Figure 2–14
w
w
w
w
Embedded Memory
shows the M4K
n Number
of Taps
Preliminary
2–21