EP1C4F324C6 Altera, EP1C4F324C6 Datasheet - Page 9
![IC CYCLONE FPGA 4K LE 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP1C4F324C6
Manufacturer Part Number
EP1C4F324C6
Description
IC CYCLONE FPGA 4K LE 324-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C4F324C6
Number Of Logic Elements/cells
4000
Number Of Labs/clbs
400
Total Ram Bits
78336
Number Of I /o
249
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1042
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C4F324C6
Manufacturer:
ALTERA
Quantity:
3
Part Number:
EP1C4F324C6
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1C4F324C6N
Manufacturer:
ALTERA
Quantity:
5 510
Company:
Part Number:
EP1C4F324C6N
Manufacturer:
ALTERA
Quantity:
250
Part Number:
EP1C4F324C6N
Manufacturer:
ALTERA
Quantity:
20 000
Logic Array
Blocks
Figure 2–2. Cyclone LAB Structure
Altera Corporation
May 2008
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local
interconnect, look-up table (LUT) chain, and register chain connection
lines. The local interconnect transfers signals between LEs in the same
LAB. LUT chain connections transfer the output of one LE's LUT to the
adjacent LE for fast sequential LUT connections within the same LAB.
Register chain connections transfer the output of one LE's register to the
adjacent LE's register within a LAB. The Quartus
associated logic within a LAB or adjacent LABs, allowing the use of local,
LUT chain, and register chain connections for performance and area
efficiency.
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM
blocks from the left and right can also drive a LAB's local interconnect
through the direct link connection. The direct link connection feature
minimizes the use of row and column interconnects, providing higher
Figure 2–2
LAB
details the Cyclone LAB.
Local Interconnect
Row Interconnect
®
II Compiler places
Logic Array Blocks
Column Interconnect
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Preliminary
2–3