EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 89

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
PLL Reconfiguration Hardware Implementation
Figure 5–20. PLL Reconfiguration Scan Chain
© December 2009
scanclkena
configupdate
scandataout
scandone
scandata
inclk
scanclk
Altera Corporation
The ability to reconfigure the PLL in real time is useful in applications that might
operate at multiple frequencies. It is also useful in prototyping environments,
allowing you to sweep PLL output frequencies and adjust the output clock phase
dynamically. For instance, a system generating test patterns is required to generate
and send patterns at 75 or 150 MHz, depending on the requirements of the device
under test. Reconfiguring PLL components in real time allows you to switch between
two such output frequencies in a few microseconds.
You can also use this feature to adjust clock-to-out (t
changing the PLL output clock phase shift. This approach eliminates the need to
regenerate a configuration file with the new PLL settings.
The following PLL components are configurable in real time:
■
■
■
■
Figure 5–20
new settings into a serial shift register chain or scan chain. Serial data shifts to the scan
chain via the scandataport, and shift registers are clocked by scanclk. The
maximum scanclk frequency is 100 MHz. After shifting the last bit of data, asserting
the configupdate signal for at least one scanclk clock cycle synchronously
updates the PLL configuration bits with the data in the scan registers.
from M counter
from N counter
/C4
Pre-scale counter (N)
Feedback counter (M)
Post-scale output counters (C0-C4)
Dynamically adjust the charge pump current (I
(R, C) to facilitate on-the-fly reconfiguration of the PLL bandwidth
shows how to adjust PLL counter settings dynamically by shifting their
/C3
PFD
/C2
LF/K/CP
/C1
CP
CO
) and loop filter components
) delays in real time by
/C0
Cyclone III Device Handbook, Volume 1
VCO
/M
F
VCO
/N
5–25