EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 3

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

MSEL Pin Connection
Table 3. Full-Rate DDR2 SDRAM Support for Cyclone III Devices
MSEL Pin Connection
Solution
Configuration Transition Current Issue
© June 2010 Altera Corporation
DDR2 SDRAM
Note to
(1) You must use 267-MHz memory component speed grade when using the Class I I/O standard and a 333-MHz memory component speed grade
(2) You must use a 200-MHz memory component speed grade.
when using the Class II I/O standard.
Table
Memory Standard
3:
1
Both Quartus II version 9.0 and 9.1 specifications refer to the DDR2 SDRAM
AFI-based PHY.
To achieve a higher clock rate in your system, refer to this Solution.
Altera has identified an issue with Cyclone III MSEL pins connected to V
high. If V
the MSEL pins may be sensed at a different setting than was intended. The device
might then require a power cycle to recover. This issue does not occur when the
device is in user mode or when configuration has started.
Connect MSEL pins to V
point then the POR circuit will reset the device. If you have already connected the
MSEL pins to V
recommended operating condition voltage level and stays within the voltage min and
max. A monotonic rise will prevent the issue from occurring.
Cyclone III EP3C25 ES Revision B and C and EP3C120 ES Revision A devices might
exhibit a momentary current surge from the V
system’s V
transition into user mode as intended. This issue will be fixed in all production
devices. While the size of the current surge is dependent on your design and on
Quartus II placement and routing, the following currents are maximums for each
device.
Table 4. Transition Current
CCIO
CCINT
EP3C120
EP3C25
Device
Cyclone III
sags below 0.75 V after power on reset and before configuration starts,
Device
CC IO
supply does not provide this current, the Cyclone III device might not
on your board, make sure that V
CCA
Speed Grade
for a logic high. If V
C8, I7, A7
C6
C7
Peak Current from V
CCINT
CCA
supply after configuration. If your
Maximum Clock Rate (MHz)
sags below the device’s POR trip
CCIO
CCINT
Single Chip Select
600 mA
rises monotonically to its
3 A
Column I/O
Cyclone III Device Family Errata Sheet
Supply During Transition
167
150
150
(1)
(2)
(1)
CCIO
for logic
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