EP2C35F672C6N Altera, EP2C35F672C6N Datasheet - Page 156

• Manufacturer Part Number: EP2C35F672C6N
• Description: IC CYCLONE II FPGA 33K 672-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C35F672C6N

• Number Of Logic Elements/cells: 33216
• Number Of Labs/clbs: 2076
• Total Ram Bits: 483840
• Number Of I /o: 475
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 33216
• # I/os (max): 475
• Frequency (max): 500MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33216
• Ram Bits: 483840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• For Use With: P0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N649-1001 - KIT DEV CYCLONE II PCI EXPRESS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1694

Timing Specifications
5–66
Cyclone II Device Handbook, Volume 1
f
f
f
t
f
clock output)
f
t
t
t
t
I N
I N P F D
I N D U T Y
I N J I T T E R
O U T _ E X T
O U T
O U T D U T Y
J I T T E R
L O C K
PLL_PSERR
Table 5–54. PLL Specifications
(to global clock)
(p-p)
Symbol
(5)
(external
(2)
Input clock frequency (–6 speed grade)
Input clock frequency (–7 speed grade)
Input clock frequency (–8 speed grade)
PFD input frequency (–6 speed grade)
PFD input frequency (–7 speed grade)
PFD input frequency (–8 speed grade)
Input clock duty cycle
Input clock period jitter
PLL output frequency (–6 speed grade)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
PLL output frequency (–6 speed grade)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
Duty cycle for external clock output (when
set to 50%)
Period jitter for external clock output
f
f
Time required to lock from end of device
configuration
Accuracy of PLL phase shift
O U T _ E X T
O U T _ E X T
PLL Timing Specifications
Table 5–54
the commercial junction temperature range (0° to 85° C), the industrial
junction temperature range (–40° to 100° C), the automotive junction
temperature range (–40° to 125° C), and the extended temperature range
(–40° to 125° C). Follow the PLL specifications for –8 speed grade devices
when operating in the industrial, automotive, or extended temperature
range.
Note (1)
> 100 MHz
≤ 100 MHz
Parameter
describes the Cyclone II PLL specifications when operating in
(Part 1 of 2)
Min
10
10
10
10
10
10
40
10
10
10
10
10
10
45
—
—
—
—
—
200
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Altera Corporation
100
402.5
402.5
402.5
402.5
Max
500
450
±60
300
(4)
(4)
(4)
60
(4)
(4)
(4)
55
30
—
February 2008
(6)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
mUI
ps
ps
μs
ps
%
%