EP2C35F672C6N Altera, EP2C35F672C6N Datasheet - Page 35

• Manufacturer Part Number: EP2C35F672C6N
• Description: IC CYCLONE II FPGA 33K 672-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C35F672C6N

• Number Of Logic Elements/cells: 33216
• Number Of Labs/clbs: 2076
• Total Ram Bits: 483840
• Number Of I /o: 475
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 33216
• # I/os (max): 475
• Frequency (max): 500MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33216
• Ram Bits: 483840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• For Use With: P0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N649-1001 - KIT DEV CYCLONE II PCI EXPRESS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1694

Figure 2–14. Global Clock Network Multiplexers
Altera Corporation
February 2007
Global Clock
Network
Clock [15 or 7..0]
Global Clock Network Distribution
Cyclone II devices contains 16 global clock networks. The device uses
multiplexers with these clocks to form six-bit buses to drive column IOE
clocks, LAB row clocks, or row IOE clocks (see
multiplexer at the LAB level selects two of the six LAB row clocks to feed
the LE registers within the LAB.
LAB row clocks can feed LEs, M4K memory blocks, and embedded
multipliers. The LAB row clocks also extend to the row I/O clock regions.
IOE clocks are associated with row or column block regions. Only six
global clock resources feed to these row and column regions.
shows the I/O clock regions.
Cyclone II Device Handbook, Volume 1
Column I/O Region
IO_CLK [5..0]
LAB Row Clock
LABCLK[5..0]
Row I/O Region
IO_CLK [5..0]
Figure
Cyclone II Architecture
2–14). Another
Figure 2–15
2–23