EP2C35F672C6 Altera, EP2C35F672C6 Datasheet - Page 34

• Manufacturer Part Number: EP2C35F672C6
• Description: IC CYCLONE II FPGA 33K 672-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C35F672C6

• Number Of Logic Elements/cells: 33216
• Number Of Labs/clbs: 2076
• Total Ram Bits: 483840
• Number Of I /o: 475
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 33216
• # I/os (max): 475
• Frequency (max): 500MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33216
• Ram Bits: 483840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• For Use With: P0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N649-1001 - KIT DEV CYCLONE II PCI EXPRESS
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1087; EP2C35F672C6ES

Global Clock Network & Phase-Locked Loops
Figure 2–13. Clock Control Block
Notes to
(1)
(2)
(3)
(4)
2–22
Cyclone II Device Handbook, Volume 1
CLK[n + 3]
CLK[n + 2]
CLK[n + 1]
CLK[n]
The CLKSWITCH signal can either be set through the configuration file or it can be dynamically set when using the
manual PLL switchover feature. The output of the multiplexer is the input reference clock (f
The CLKSELECT[1..0] signals are fed by internal logic and can be used to dynamically select the clock source for
the global clock network when the device is in user mode.
The static clock select signals are set in the configuration file and cannot be dynamically controlled when the device
is in user mode.
Internal logic can be used to enabled or disabled the global clock network in user mode.
Figure
2–13:
inclk1
inclk0
Static Clock Select (3)
CLKSWITCH (1)
Of the sources listed, only two clock pins, two PLL clock outputs, one
DPCLK pin, and one internally-generated signal are chosen to drive into a
clock control block.
clock control block. Out of these six inputs, the two clock input pins and
two PLL outputs can be dynamic selected to feed a global clock network.
The clock control block supports static selection of DPCLK and the signal
from internal logic.
f
IN
PLL
Internal Logic
DPCLK or
CDPCLK
C0
C1
C2
Figure 2–13
(3)
CLKSELECT[1..0] (2)
shows a more detailed diagram of the
Clock Control Block
Static Clock
Select (3)
CLKENA (4)
IN
Enable/
Disable
Altera Corporation
) for the PLL.
February 2007
Global
Clock