EP2C70F896I8 Altera, EP2C70F896I8 Datasheet - Page 146

• Manufacturer Part Number: EP2C70F896I8
• Description: IC CYCLONE II FPGA 70K 896-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C70F896I8

• Number Of Logic Elements/cells: 68416
• Number Of Labs/clbs: 4276
• Total Ram Bits: 1152000
• Number Of I /o: 622
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 896-FBGA
• For Use With: P0304 - DE2-70 CALL FOR ACADEMIC PRICING544-1703 - VIDEO KIT W/CYCLONE II EP2C70N544-1699 - DSP KIT W/CYCLONE II EPS2C70N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-2146

Timing Specifications
Figure 5–3. High-Speed I/O Timing Diagram
5–56
Cyclone II Device Handbook, Volume 1
Sampling window
Receiver input skew
margin
Input jitter (peak to peak)
Output jitter (peak to peak)
Signal rise time
Signal fall time
Lock time
Table 5–47. High-Speed I/O Timing Definitions (Part 2 of 2)
Parameter
Internal Clock
Input Clock
Input Data
Receiver
External
SW
RSKM
t
t
t
R I S E
FA L L
L O C K
Symbol
Figure 5–4
TCCS
—
—
The period of time during which the data must be valid in order for you
to capture it correctly. Sampling window is the sum of the setup time,
hold time, and jitter. The window of t
in the sampling window.
SW = TUI – TCCS – (2 × RSKM)
RSKM is defined by the total margin left after accounting for the
sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Low-to-high transmission time.
High-to-low transmission time.
Lock time for high-speed transmitter and receiver PLLs.
RSKM
shows the high-speed I/O timing budget.
Sampling Window (SW)
Time Unit Interval (TUI)
Description
SU
RSKM
+ t
H
is expected to be centered
TCCS
Altera Corporation
February 2008