EP2S30F484C3N Altera, EP2S30F484C3N Datasheet - Page 22
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EP2S30F484C3N
Manufacturer Part Number
EP2S30F484C3N
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F484C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
No. Of Macrocells
33880
Family Type
Stratix II
No. Of I/o's
342
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
550MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1890
EP2S30F484C3N
EP2S30F484C3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F484C3N
Manufacturer:
ALTERA
Quantity:
591
Part Number:
EP2S30F484C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Adaptive Logic Modules
Figure 2–10. Template for Supported Seven-Input Functions in Extended LUT Mode
Note to
(1)
2–14
Stratix II Device Handbook, Volume 1
If the seven-input function is unregistered, the unused eighth input is available for register packing. The second
register, reg1, is not available.
Figure
datae0
datae1
dataf0
dataf1
datac
dataa
datab
datad
(1)
2–10:
This input is available
for register packing.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An ALM in
arithmetic mode uses two sets of two four-input LUTs along with two
dedicated full adders. The dedicated adders allow the LUTs to be
available to perform pre-adder logic; therefore, each adder can add the
output of two four-input functions. The four LUTs share the dataa and
datab inputs. As shown in
adder0, and the carry-out from adder0 feeds to carry-in of adder1. The
carry-out from adder1 drives to adder0 of the next ALM in the LAB.
ALMs in arithmetic mode can drive out registered and/or unregistered
versions of the adder outputs.
5-Input
5-Input
LUT
LUT
combout0
Figure
2–11, the carry-in signal feeds to
D
reg0
Q
To general or
To general or
local routing
local routing
Altera Corporation
May 2007