EP2S30F484C3N Altera, EP2S30F484C3N Datasheet - Page 235
![IC STRATIX II FPGA 30K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S30F484C3N
Manufacturer Part Number
EP2S30F484C3N
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F484C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
No. Of Macrocells
33880
Family Type
Stratix II
No. Of I/o's
342
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
550MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1890
EP2S30F484C3N
EP2S30F484C3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F484C3N
Manufacturer:
ALTERA
Quantity:
591
Part Number:
EP2S30F484C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
April 2011
January 2005,
v2.0
October 2004,
v1.2
July 2004, v1.1
February 2004,
v1.0
Table 5–103. Document Revision History (Part 3 of 3)
Document
Date and
Version
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Added document to the Stratix II Device Handbook.
Updated the “Power Consumption” section.
Added the “High-Speed I/O Specifications” and
“On-Chip Termination Specifications” sections.
Removed the ESD Protection Specifications
section.
Updated Tables 5–3 through 5–13, 5–16 through
5–18, 5–21, 5–35, 5–39, and 5–40.
Updated tables in “Timing Model” section.
Added Tables 5–30 and 5–31.
Updated Table 5–3.
Updated introduction text in the “PLL Timing
Specifications” section.
Re-organized chapter.
Added typical values and C
Added undershoot specification to Note (4) for
Tables 5–1 through 5–9.
Added Note (1) to Tables 5–5 and 5–6.
Added V
Added “I/O Timing Measurement Methodology”
section.
Added Table 5–72.
Updated Tables 5–1 through 5–2 and Tables 5–24
through 5–29.
I D
and V
Changes Made
I C M
to Table 5–10.
O U T F B
to Table 5–32.
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Summary of Changes
—
—
—
—
5–99
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