EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 383

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

Chapter 11: Configuring Stratix III Devices
Chapter Revision History
Chapter Revision History
Table 11–17. Chapter Revision History (Part 1 of 2)
© March 2011 Altera Corporation
March 2011
July 2010
March 2010
May 2009
February 2009
October 2008
Date
Table 11–17
Version
2.0
1.9
1.8
1.7
1.6
1.5
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Updated for the Quartus II software version 9.1 SP2 release:
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lists the revision history for this chapter.
Updated the
Active Serial Configuration (Serial Configuration
Using a MAX II Device as an External Host”
Updated
Updated Table 11–14.
Updated “FPP Configuration Using a MAX II Device as an External Host” on
page 11–8.
Added Figure 11–11.
Updated Figure 11–6, Figure 11–7, Figure 11–16, Figure 11–19, and Figure 11–20.
Updated “Estimating Active Serial Configuration Time” section.
Added Table 11–8.
Updated Table 11–8, Table 11–13, and Table 11–14.
Removed “Conclusion” section.
Updated Table 11–1, Table 11–2, Table 11–5, Table 11–6, Table 11–9, and
Table 11–13.
Updated Figure 11–6, Figure 11–16, Figure 11–17, Figure 11–18, Figure 11–19,
and Figure 11–20.
Updated “PS Configuration Using a Microprocessor”, “PS Configuration Using a
Download Cable”, and “JTAG Configuration” sections.
Removed Figure 11-12 Fast AS Configuration Timing.
Removed Table 11-8 Fast AS Timing Parameters for Stratix III devices.
Updated Figure 11–6, Figure 11–7, Figure 11–12, and Figure 11–16.
Removed “Referenced Documents” section.
Updated “FPP Configuration Using a MAX II Device as an External Host”, “Fast
Active Serial Configuration (Serial Configuration Devices)”, “JTAG Configuration”,
“Power-On Reset Circuit”, “PS Configuration Using a MAX II Device as an External
Host”, and “PS Configuration Using a Download Cable” sections.
Updated Table 11–13 and Table 11–14.
Updated New Document Format.
Updated (Note 3) to Figure 11–17.
Updated (Note 3) to Figure 11–18.
Updated (Note 3) to Figure 11–19.
Updated (Note 3) to Figure 11–20.
Table
“FPP Configuration Using a MAX II Device as an External
11–14.
Changes Made
Devices)”, and
Stratix III Device Handbook, Volume 1
“PS Configuration
Host”,
“Fast
11–51